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SBASAY9 October 2025 AMC0306M05-Q1

PRODMIX

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

DWV|8

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.13 Electrical Characteristics

minimum and maximum specifications are at T_A = –40°C to 125°C, AVDD = 3.0V to 5.5V, DVDD = 2.7V to 5.5V, V_INP = –50mV to 50mV, V_INN = 0V, and sinc³ filter with OSR = 256 (unless otherwise noted); typical specifications are at T_A = 25°C, f_CLKIN = 20MHz with 50% duty cycle, AVDD = 5V, and DVDD = 3.3V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
C_IN	Effective input sampling capacitance			7.7		pF
R_IN	Input impedance	f_CLK = 10MHz	11	13	15	kΩ
R_IN	Input impedance	f_CLK = 20MHz	5.5	6.5	7.5	kΩ
I_INP	Input current	V_IN = (V_INP – V_INN) = V_{FSR, MAX}, f_CLK = 10MHz		4		μA
I_INP	Input current	V_IN = (V_INP – V_INN) = V_{FSR, MAX}, f_CLK = 20MHz		8		μA
I_INN	Input current	V_IN = (V_INP – V_INN) = V_{FSR, MAX}, f_CLK = 10MHz		–4		μA
I_INN	Input current	V_IN = (V_INP – V_INN) = V_{FSR, MAX}, f_CLK = 20MHz		–8		μA
CMTI	Common-mode transient immunity		150			V/ns
DC ACCURACY
E_O	Offset error	INP = INN = AGND, T_A = 25°C	–200	10	200	μV
TCE_O	Offset error temperature drift⁽³⁾		–1.2		1.2	μV/°C
E_G	Gain error⁽¹⁾	T_A = 25°C	–0.3%	±0.04%	0.3%
TCE_G	Gain error temperature drift⁽⁴⁾		–50	±20	50	ppm/°C
INL	Integral nonlinearity⁽²⁾	Resolution: 16 bits	–6	±1	6	LSB
DNL	Differential nonlinearity	Resolution: 16 bits	–0.99		0.99	LSB
CMRR	Common-mode rejection ratio	INP = INN, f_IN = 0Hz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–99		dB
CMRR	Common-mode rejection ratio	INP = INN, f_IN from 0.1Hz to 10kHz, V_{CM min} ≤ V_IN ≤ V_{CM max}		–100		dB
PSRR	Power-supply rejection ratio	INP = INN = AGND, AVDD from 3.0V to 5.5V, DC		–100		dB
PSRR	Power-supply rejection ratio	INP = INN = AGND, AVDD from 3.0V to 5.5V, 10kHz / 100mV ripple		–100		dB
AC ACCURACY
SNR	Signal-to-noise ratio	f_IN = 1kHz		84		dB
SINAD	Signal-to-noise + distortion	f_IN = 1kHz		84		dB
THD	Total harmonic distortion⁽⁵⁾	3.0V ≤ AVDD ≤ 5.5V, f_IN = 1kHz, 5MHz ≤ f_CLKIN ≤ 21MHz		–103	–79	dB
DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)
I_IN	Input current	DGND ≤ V_IN ≤ DVDD	0		7	μA
C_IN	Input capacitance			4		pF
V_IH	High-level input voltage		0.7 × DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.3 × DVDD	V
DIGITAL OUTPUT (CMOS)
C_LOAD	Output load capacitance			15	30	pF
V_OH	High-level output voltage	I_OH = –4mA	DVDD – 0.4			V
V_OL	Low-level output voltage	I_OL = 4mA			0.4	V
POWER SUPPLY
I_AVDD	High-side supply current			6.2	8.0	mA
I_DVDD	Low-side supply current	C_LOAD = 15pF		4.5	7.0	mA
AVDD_UV	High-side undervoltage detection threshold	AVDD rising	2.4	2.6	2.8	V
AVDD_UV	High-side undervoltage detection threshold	AVDD falling	1.9	2.05	2.2	V
DVDD_UV	Low-side undervoltage detection threshold	DVDD rising	2.3	2.5	2.7	V
DVDD_UV	Low-side undervoltage detection threshold	DVDD falling	1.9	2.05	2.2	V

(1) This parameter is input referred.

(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(3) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCE_O = (E_O,MAX – E_O,MIN) / TempRange where E_O,MAX and E_O,MIN refer to the maximum and minimum E_O values measured within the temperature range (–40 to 125℃).

(4) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCE_G (ppm) = ((E_G,MAX - E_G,MIN) / TempRange) x 10⁴ where E_G,MAX and E_G,MIN refer to the maximum and minimum E_G values (in %) measured within the temperature range (–40 to 125℃).

(5) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.