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ZHCSGC8A March 2014 – June 2017 AFE5401-Q1

PRODUCTION DATA.

封裝選項(xiàng)

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage range	DRVDD to DRVSS	–0.3	+3.8	V
	AVDD3 to AVSS	–0.3	+3.8
	AVDD18 to AVSS	–0.3	+2.2
	DVDD18 to DVSS	–0.3	+2.2
Voltage between	AVSS and DVSS	–0.3	+0.3	V
	AVSS and DRVSS	–0.3	+0.3
	DVSS and DRVSS	–0.3	+0.3
Clock input pins (CLKINP and CLKINM) to AVSS		–0.3	minimum (2.2, AVDD18 + 0.3)	V
Analog input pins (IN_IP, IN_IM, IN_IP_AUX, and IN_IM_AUX) to AVSS		–0.3	minimum (2.2, AVDD18 + 0.3)	V
Digital control pins to DVSS	STBY, RESET, SCLK, SDATA, SEN, TRIG	–0.3	+3.6	V
Maximum operating junction temperature, T_J max			+125	°C
Storage temperature, T_stg		–60	+150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
TEMPERATURE
T_A	Ambient temperature range		–40		+105	°C
SUPPLIES
DRVDD	Output driver supply		1.7		3.6	V
AVDD3	3-V analog supply voltage		3	3.3	3.6	V
AVDD18	1.8-V analog supply voltage		1.7	1.8	1.9	V
DVDD18	1.8-V digital supply voltage		1.7	1.8	1.9	V
CLOCK INPUT
CLKIN	Input clock frequency	Default mode (DIV_EN disabled)	12.5		25	MHz
		With DIV_EN, DIV_FRC enabled and DIV_REG = 1	25		50
		With DIV_EN, DIV_FRC enabled and DIV_REG = 2	37.5		75
		With DIV_EN, DIV_FRC enabled and DIV_REG = 3	50		100
		With decimate-by-2 or decimate-by-4 modes enabled (DIV_EN disabled)⁽¹⁾	12.5		50
V_CLKINP – V_CLKINM	Input clock amplitude differential	Sine wave, ac-coupled	0.2	1.5		V_PP
		LVPECL, ac-coupled	0.2	1.6
		LVDS, ac-coupled	0.2	0.7
	Single-ended CMOS clock on CLKINP with CLKINM connected to AVSS			1.8		V
	Input clock duty cycle		40%		60%
DIGITAL OUTPUT
C_LOAD	Tolerable external load capacitance from each output pin to DRVSS			5		pF

(1) In decimation mode, input clock frequency (CLKIN) can be scaled up to maximum of 200 MHz with the input divider.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		AFE5401-Q1	UNIT
		RGC (VQFN)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	24.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	8.7	°C/W
R_θJB	Junction-to-board thermal resistance	3.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	3.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with a 0.1-µF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise noted. Typical values are at T_NOM = +25°C.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
FULL-CHANNEL CHARACTERISTICS
	Maximum differential input signal amplitude on IN_IP and IN_IM	LNA gain = 12 dB			0.5		V_PP
		LNA gain = 15 dB (default)			0.35
		LNA gain = 16.5 dB			0.3
		LNA gain = 18 dB			0.25
	Input resistance, from each input to internal dc bias level	Default		1 ± 20%			kΩ
	Input resistance, from each input to internal dc bias level	TERM_INT_20K_LNA / TERM_INT_20K_AUX = 1		10 ± 20%			kΩ
C_I	Input capacitance	Differential input capacitance			5.5		pF
V_VCM	VCM output voltage	Voltage on VCM pins			1.45		V
	VCM output current capability	For 50-mV drop in VCM voltage			3		mA
	Gain matching	Across channels and devices			0.15	1	dB
E_G	Gain error	PGA gain = 30 dB			± 0.6	± 1.4	dB
E_O	Offset error	PGA gain = 30 dB, 1 sigma value			± 120		LSB
	Input-referred noise voltage	f_IN = 3 MHz, idle channel, PGA gain = 30 dB (default)			2.9	3.8	nV/√Hz
	Input-referred noise voltage	f_IN = 3 MHz, idle channel, PGA gain = 30 dB (HIGH_POW_LNA mode)			2.5		nV/√Hz
SNR	Signal-to-noise ratio	f_IN = 3 MHz, main channel		65	67.7		dBFS
SNR	Signal-to-noise ratio	f_IN = 3 MHz, AUX channel			69.2		dBFS
SFDR	Spurious-free dynamic range	f_IN = 3 MHz, main channel (default)		57	66		dBc
SFDR	Spurious-free dynamic range	f_IN = 3 MHz, main channel (HPL_EN mode)			74		dBc
THD	Total harmonic distortion	f_IN = 3 MHz, main channel		56	65		dBc
IMD	Intermodulation distortion	f_IN1 = 1.5 MHz, f_IN2 = 2 MHz, A_IN1 and A_IN2 = –7 dBFS			83		dBFS
PSRR	Power-supply rejection ratio	For a 50-mV_PP signal on AVDD18 up to 10 MHz, no input applied to analog inputs			> 50		dB
	Number of bits in the ADC				12		Bits
	Crosstalk, main channel to main channel	Aggressor channel: f_IN = 2 MHz, 1 dB below ADC full-scale. Victim channel: f_IN= 3 MHz, 1 dB below ADC full-scale.			70		dB
	Maximum channel gain	LNA gain = 18 dB, PGA gain = 30 dB			48		dB
	Minimum channel gain	LNA gain = 12 dB, PGA gain = 0 dB			12		dB
	PGA gain resolution				3		dB
	PGA gain range	Maximum PGA gain – minimum PGA gain			30		dB
	Differential input voltage range for AUX channel				2		V_PP
ANTIALIAS FILTER (Third-Order Elliptic)
f_C	3-dB filter corner frequency	FILTER_BW = 0 (default)			8		MHz
		FILTER_BW = 1			7
		FILTER_BW = 2			10.5
		FILTER_BW = 3			12
	3-dB filter corner frequency tolerance	For all FILTER_BW settings			±5%
ATT_2FC	Filter attenuation	At 2 × f_C			30		dBc
ATT_STPBND	Filter attenuation	Stop-band attenuation (f_IN > 2.25 × f_C)			40		dBc
RP_PSBND	Ripple in pass band				1.5		dB
POWER
	Total core power, per channel	Idle channel, excluding DRVDD power			64		mW
I_AVDD18	AVDD18 current consumption	Default mode			131	145	mA
		With HIGH_POW_LNA mode enabled			153
		With HPL_EN mode enabled			135
I_AVDD3	AVDD3 current consumption				1.5	3.5	mA
I_DVDD18	DVDD18 current consumption				8	12	mA
I_DRVDD	DRVDD current consumption	5-pF load, toggle data test pattern mode	DRVDD = 3.3 V		14		mA
		5-pF load, toggle data test pattern mode	DRVDD = 1.8 V		8.5
		15-pF load, toggle data test pattern mode	DRVDD = 3.3 V		36
		15-pF load, toggle data test pattern mode	DRVDD = 1.8 V		20
	Power-down				5		mW
	STBY power				15		mW

6.6 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, unless otherwise noted. Typical values are at T_NOM = +25°C.

PARAMETER		MIN	TYP	MAX	UNIT
DIGITAL INPUTS (STBY, RESET, SCLK, CLKIN, SDATA, SEN, TRIG)⁽¹⁾
V_IH	High-level input voltage	1.4			V
V_IL	Low-level input voltage			0.4	V
I_IH	High-level input current		10		µA
I_IL	Low-level input current		10		µA
C_I	Input capacitance		4		pF
V_{IL_CLKINP}	Input clock CMOS single-ended (V_CLKINP), V_CLKINM connected to AVSS	0.25 × AVDD18			V
V_{IH_CLKINP}		0.75 × AVDD18			V
DIGITAL OUTPUTS
V_OH	High-level output voltage	DRVDD – 0.2	DRVDD		V
V_OL	Low-level output voltage		0	0.2	V

(1) The SEN pin has an internal 150-kΩ pull-up resistor. The STBY, RESET, SCLK, SDATA, and TRIG pins have an internal 150-kΩ pull-down resistor.

6.7 Timing Requirements: Output Interface

Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with 0.1 µF, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise noted. Typical values are at T_NOM = +25°C.

			MIN	NOM	MAX	UNIT
t_ADLY	Aperture delay between the rising edge of the input sampling clock and the actual time at which the sampling occurs			3		ns
	Wake-up time	Time to valid data after coming out of STANDBY mode		500		µs
		Time to valid data after coming out of GLOBAL_PDN mode		2		ms
		Time to valid data after stopping and restarting the input clock		500		µs
t_LAT	ADC latency (default, after reset)			10.5		t_{AFE_CLK} cycles
t_SU	Data setup time	Data valid⁽¹⁾ to 50% of DCLK rising edge, DRVDD = 3.3 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0	4.1			ns
t_SU	Data setup time	Data valid⁽¹⁾ to 50% of DCLK rising edge, DRVDD =1.8 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 5	3.7			ns
t_HO	Data hold time	50% of DCLK rising edge to data becoming invalid⁽¹⁾, DRVDD = 3.3 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0	2.8			ns
t_HO	Data hold time	50% of DCLK rising edge to data becoming invalid⁽¹⁾, DRVDD = 1.8 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 5	2.7			ns
t_R, t_F	CMOS output data and clock rise and fall time	DRVDD = 3.3 V, load = 5 pF, 10% to 90%, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0		1.2		ns
t_R, t_F	CMOS output data and clock rise and fall time	DRVDD = 1.8 V, load = 5 pF, 10% to 90%, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 5		1.1		ns
t_OUT	Delay from CLKIN rising edge to DCLK rising edge, zero-crossing of input clock to 50% of DCLK rising edge, DRVDD = 3.3 V, load = 5 pF, 4x serialization, STR_CTRL_CLK and STR_CTRL_CLK_DATA = 0		6.7		9.5	ns
t_{S_TRIG}	TRIG setup time, TRIG pulse duration ≥ t_{AFE_CLK}		4			ns
t_{H_TRIG}	TRIG hold time, TRIG pulse duration ≥ t_{AFE_CLK}		3			ns

(1) Data valid refers to a logic high of 0.7 × DRVDD and a logic low of 0.3 × DRVDD.

6.8 Timing Requirements: RESET

Typical values are at T_A = +25°C. Minimum and maximum specifications are across the full temperature range of T_MIN = –40°C to T_MAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	UNIT
t₁	Power-on to reset delay	Delay from power-up of AVDD18 and DVDD18 to RESET pulse active		1	ms
t₂	Reset pulse duration	Pulse duration of active RESET signal	40		ns
t₃	Register write delay	Delay from RESET disable to SEN active	100		ns

6.9 Timing Requirements: Serial Interface Operation

Minimum specifications are across the full temperature range of T_MIN = –40°C to T_MAX = +105°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, and DVDD18 = 1.8 V, C_LOAD on SDOUT = 5 pF, unless otherwise noted.

PARAMETER		MIN	TYP	MAX	UNIT
t₁	SCLK period	50			ns
t₂	SCLK high time	20			ns
t₃	SCLK low time	20			ns
t₄	Data setup time	5			ns
t₅	Data hold time	5			ns
t₆	SEN falling to SCLK rising	8			ns
t₇	Time between last SCLK rising edge to SEN rising edge	8			ns
t₈	Delay from SCLK falling edge to SDOUT valid	7	11	15	ns

NOINDENT:

t_CLK = 1 / f_CLKIN

Figure 1. Output Interface Timing Diagram

A high pulse on the RESET pin is required for register initialization through the reset pin. Figure 2 shows the timing requirement for reset after power-up.

Figure 2. Reset Timing

AFE5401-Q1 Srl_Intrfc_Rgstr_Wrt_bas619.gif

Figure 3. Serial Interface Register Write Timing Diagram

AFE5401-Q1 Srl_Intrfc_Rgstr_Rd_bas619.gif

Figure 4. Serial Interface Register Readout Timing Diagram

6.10 Typical Characteristics

Typical values are at T_A = +25°C, AVDD18 = DVDD18 = 1.8 V, AVDD3 = DRVDD = 3.3 V, –1-dBFS analog input ac-coupled with a 0.1-μF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, antialiasing filter corner frequency = 8 MHz, and differential input sine wave clock with 50% duty cycle, unless otherwise noted.

SNR = 67.7 dBFS

SFDR = 65.7 dBc

THD = 65.2 dBc

Figure 5. FFT for 3-MHz, –1-dBFS Input Signal,
0-dB PGA Gain (Sample Rate = 25 MSPS)

f_IN1 = 1.5 MHz	Each Tone at –7-dBFS Amplitude
f_IN2 = 2 MHz	Two-Tone IMD = –83 dBFS

Figure 7. FFT with Two-Tone Signal

Figure 9. Signal-to-Noise Ratio vs Input Signal Frequency (PGA Gain = 0 dB)

Figure 11. Signal-to-Noise Ratio vs PGA Gain

Figure 13. Signal-to-Noise Ratio,
Spurious-Free Dynamic Range vs
Input Signal Amplitude (PGA Gain = 0 dB)

Figure 15. Signal-to-Noise Ratio vs Input Clock Amplitude (PGA Gain = 0 dB)

Figure 17. Signal-to-Noise Ratio vs Input Clock Duty Cycle (PGA Gain = 0 dB)

Figure 19. Signal-to-Noise Ratio vs Sampling Frequency (PGA Gain = 0 dB)

Figure 21. Spurious-Free Dynamic Range vs Sampling Frequency (PGA Gain = 0 dB)

Figure 23. Signal-to-Noise Ratio vs AVDD18 and Temperature (PGA Gain = 0 dB)

Figure 25. Spurious-Free Dynamic Range vs AVDD18 and Temperature (PGA Gain = 0 dB, Default Mode)

Figure 27. Spurious-Free Dynamic Range vs AVDD18 and Temperature (PGA Gain = 0 dB, HPL_EN = 1)

Figure 29. Signal-to-Noise Ratio vs LNA Gain
(PGA Gain = 30 dB)

Figure 31. Input-Referred Noise vs LNA Gain
(PGA Gain = 30 dB)

Figure 33. Input-Referred Noise vs
PGA Gain and Temperature

Figure 35. Output-Referred Noise vs
PGA Gain and Temperature

Figure 37. Gain Matching Histogram (Maximum Gain Difference Among the Four Channels within a Device)

Figure 39. Offset Error Histogram at PGA Gain = 30 dB

Figure 41. Antialias Filter Response vs
FILTER_BW Settings (PGA Gain = 30 dB)

Figure 43. Antialias Filter Response vs Temperature (PGA Gain = 0 dB, FILTER_BW = 8 MHz)

Figure 45. Antialias Filter Response for Equalizer Modes (PGA Gain = 30 dB)

Figure 47. Antialias Filter Response for
Equalizer Modes across Temperature (PGA Gain = 30 dB)

Figure 49. Decimate-by-2 Filter Response (Sampling Frequency = 50 MHz)

Figure 51. Temperature Sensor Response

Figure 53. DVDD18 Supply Current vs Sampling Frequency

Figure 55. DRVDD Supply Current vs Sampling Frequency (15-pF Load with Toggle Test Mode)

SNR = 53.3 dBFS

SFDR = 63.7 dBc

THD = 63.6 dBc

Figure 6. FFT for 3-MHz, –1-dBFS Input Signal,
30-dB PGA Gain (Sample Rate = 25 MSPS)

Figure 8. Spurious-Free Dynamic Range vs
Input Signal Frequency

Figure 10. Signal-To-Noise Ratio vs Input Signal Frequency (PGA Gain = 30 dB)

Figure 12. Spurious-Free Dynamic Range vs PGA Gain

Figure 14. Signal-to-Noise Ratio,
Spurious-Free Dynamic Range vs
Input Signal Amplitude (PGA Gain = 30 dB)

Figure 16. Spurious-Free Dynamic Range vs
Input Clock Amplitude (PGA Gain = 0 dB)

Figure 18. Spurious-Free Dynamic Range vs
Input Clock Amplitude (PGA Gain = 0 dB)

Figure 20. Signal-to-Noise Ratio vs Sampling Frequency (PGA Gain = 30 dB)

Figure 22. Spurious-Free Dynamic Range vs Sampling Frequency (PGA Gain = 30 dB)

Figure 24. Signal-to-Noise Ratio vs AVDD18 and Temperature (PGA Gain = 30 dB)

Figure 26. Spurious-Free Dynamic Range vs AVDD18 and Temperature (PGA Gain = 30 dB, Default Mode)

Figure 28. Spurious-Free Dynamic Range vs AVDD18 and Temperature (PGA Gain = 30 dB, HPL_EN = 1)

Figure 30. Spurious-Free Dynamic Range vs LNA Gain
(PGA Gain = 30 dB)

Figure 32. Input-Referred Noise vs PGA Gain

Figure 34. Output-Referred Noise vs PGA Gain

Figure 36. Gain Error Histogram for PGA Gain = 30 dB

Figure 38. Channel Offset vs
PGA Gain for Two Typical Devices

Figure 40. Antialias Filter Response vs
FILTER_BW Settings (PGA Gain = 0 dB)

Figure 42. Antialias Filter Response vs AVDD18
(PGA Gain = 0 dB, FILTER_BW = 8 MHz)

Figure 44. Antialias Filter Response for Equalizer Modes (PGA Gain = 0 dB)

Figure 46. Antialias Filter Response for
Equalizer Modes across Temperature (PGA Gain = 0 dB)

SNR = 69.2 dBFS	SFDR = 69.8 dBc	THD = 69.7 dBc

Figure 48. FFT for AUX Channel
(3-MHz, –1-dBFS Input Signal, Sample Rate = 25 MSPS)

Figure 50. Decimate-by-4 Filter Response (Sampling Frequency = 12.5 MHz)

Figure 52. AVDD18 Supply Current vs Sampling Frequency

Figure 54. AVDD3 Supply Current vs Sampling Frequency

Figure 56. AFE Core Power, Channel Excluding DRVDD