ZHCSNC4B February 2021 – September 2022 ADC3661 , ADC3662 , ADC3663
PRODUCTION DATA
After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin, as shown in Figure 9-6.
| MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|
| t1 | Power-on delay: delay from power up to logic level of REFBUF pin | 2 | ms | ||
| t2 | Delay from REFBUF pin logic level to RESET rising edge | 100 | ns | ||
| t3 | RESET pulse width | 1 | us | ||
| t4 | Delay from RESET disable to SEN active | ~ 200000 | clock cycles | ||