ZHCSLJ1C July 2020 – December 2022 ADC3541 , ADC3542 , ADC3543
PRODUCTION DATA
In parallel CMOS mode, the ADC354x device supports complex decimation output with DDR CMOS interface and real output with SDR and DDR CMOS interface as shown in Figure 8-36 (complex decimation) and Figure 8-37 (real decimation). In this illustration the output format is selected to 16-bit.
Table 8-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on complex decimation setting (N).
Furthermore the table shows an actual lane rate example with complex decimation by 4.
| REAL/COMPLEX DECIMATION | DECIMATION SETTING | ADC SAMPLING RATE | DCLK | DOUT (MHz) |
|---|---|---|---|---|
| Complex | N | FS | FS x 2 / N | FS x 4 / N |
| 4 | 65 MHz | 32.5 MHz | 65 MHz |
Table 8-4 illustrates the output interface data rate along with the corresponding DCLK frequency based on real decimation setting (M).
Furthermore the table shows an actual lane rate example with complex decimation by 4.
| REAL/COMPLEX DECIMATION | DECIMATION SETTING | ADC SAMPLING RATE | SDR/DDR CMOS | DCLK | DOUT |
|---|---|---|---|---|---|
| Real | M | FS | SDR | FS / M | FS / M |
| DDR | FS x 2 / M | ||||
| 4 | 65 MHz | SDR | 16.25 MHz | 16.25 MHz | |
| DDR | 32.5 MHz |