ZHCSEU3E July 2014 – June 2022 ADC3221 , ADC3222 , ADC3223 , ADC3224
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | LOW SPEED ENABLE | |
| W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h |
| LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | 0 | W | 0h | Must write 0 |
| 1-0 | LOW SPEED ENABLE | R/W | 0h | Enables low speed operation in 1-wire and 2-wire mode. Depending upon sampling frequency, write this bit as per Table 8-20. |
| fS (MSPS) | REGISTER BIT LOW SPEED ENABLE | ||
|---|---|---|---|
| MIN | MAX | 1-WIRE MODE | 2-WIRE MODE |
| 25 | 125 | 00 | 00 |
| 20 | 25 | 10 | 11 |
| 15 | 20 | 10 | Not supported |