ZHCSEU3E July 2014 – June 2022 ADC3221 , ADC3222 , ADC3223 , ADC3224
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN) | |||||||
| VIH | High-level input voltage | All digital inputs support 1.8-V and 3.3-V CMOS logic levels | 1.3 | V | |||
| VIL | Low-level input voltage | All digital inputs support 1.8-V and 3.3-V CMOS logic levels | 0.4 | V | |||
| IIH | High-level input current | RESET, SDATA, SCLK, PDN | VHIGH = 1.8 V | 10 | μA | ||
| SEN(1) | VHIGH = 1.8 V | 0 | |||||
| IIL | Low-level input current | RESET, SDATA, SCLK, PDN | VLOW = 0 V | 0 | μA | ||
| SEN | VLOW = 0 V | 10 | |||||
| DIGITAL INPUTS (SYSREFP, SYSREFM) | |||||||
| Differential swing | 0.2 | 0.8 | 1 | V | |||
| Common-mode voltage for SYSREF(2) | 0.9 | V | |||||
| DIGITAL OUTPUTS, CMOS INTERFACE (SDOUT) | |||||||
| VOH | High-level output voltage | DVDD – 0.1 | DVDD | V | |||
| VOL | Low-level output voltage | 0 | 0.1 | V | |||
| DIGITAL OUTPUTS, LVDS INTERFACE | |||||||
| VODH | High-level output differential voltage | With an external 100-Ω termination | 280 | 350 | 460 | mV | |
| VODL | Low-level output differential voltage | With an external 100-Ω termination | –460 | –350 | –280 | mV | |
| VOCM | Output common-mode voltage | 1.05 | V | ||||