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ZHCSOI5A October 2021 – November 2024 ADC12DJ1600 , ADC12QJ1600 , ADC12SJ1600

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

AAV|144
- MPBGAM2C

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.9 Switching Characteristics

typical values at T_A = 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (V_FS = 0.8 V_PP), f_IN = 97 MHz, A_IN = –1 dBFS, f_CLK =1.6 GHz, filtered 1-V_PP sine-wave clock applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration, SER_PE = 4 (unless otherwise noted); VA11Q and VCLK11 noise suppression on when CPLL on; minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ADC SAMPLING CLOCK
t_AD	Sampling (aperture) delay from the clock falling edge to sampling instant	PLL disabled, CLK±		305		ps
		PLL enabled, CLK±		314		ps
		PLL enabled, SE_CLK		332		ps
t_AJ	Aperture jitter, rms	Dither disabled (ADC_DITH_EN = 0)		50		fs
t_AJ	Aperture jitter, rms	Dither enabled (ADC_DITH_EN = 1)		60		fs
t_J(PLL)	PLL additive jitter, rms	PLL enabled (PLL_EN = 1), f_PLLREF = 50 MHz		358		fs
t_J(PLL)	PLL additive jitter, rms	PLL enabled (PLL_EN = 1), f_PLLREF = 200 MHz		340		fs
CLOCK AND TRIGGER OUTPUTS (PLLREFO±, TRIGOUT±, ORC, ORD)
f_PLLREFO	PLLREFO± frequency range	PLL Enabled, PLLREFO± enabled	50		500	MHz
f_DIVREFO	ORC and ORD frequency range when programmed to output divided PLL reference clock	PLL Enabled, DIVREF_C_MODE > 0, DIVREF_D_MODE > 0	12.5		100	MHz
t_PW(TRIGOUT)	Minimum TRIGOUT± pulse width	TRIGOUT_SRC = 0 (TMSTP±)		1		t_CLK
f_TRIGOUT	TRIGOUT± frequency range	TRIGOUT_SRC = 1 (S-PLL)			800	MHz
t_PD(REF)	Input clock to PLLREFO± propagation delay	PLLREF_SE = 0 (CLK± used), nominal supply voltage, T_A = 25°C	280	359	440	ps
t_PD(REF)	Input clock to PLLREFO± propagation delay	PLLREF_SE = 1 (SE_CLK used), nominal supply voltage, T_A = 25°C	380	469	560	ps
t_PD-TEMPCO	Input clock to PLLREFO± propagation delay temperature coefficient	PLLREF_SE = 0 (CLK± used), nominal supply voltage	250	330	420	fs/°C
t_PD-TEMPCO		PLLREF_SE = 1 (SE_CLK used), nominal supply voltage	280	365	450	fs/°C
t_PD-VOLTCO	Input clock to PLLREFO± propagation delay supply voltage coefficient	PLLREF_SE = 0 (CLK± used), T_A = 25°C	–533	–397	–186	fs/mV
t_PD-VOLTCO		PLLREF_SE = 1 (SE_CLK used), T_A = 25°C	–480	–372	–180	fs/mV
SERIAL DATA OUTPUTS (D[7:0]+, D[7:0]–)
f_SERDES	Serialized output bit rate		2.5		17.16	Gbps
UI	Serialized output unit interval		58.3		400	ps
t_TLH	Low-to-high transition time (differential)	20% to 80%, 8H8L test pattern, 16.5 Gbps		28		ps
t_THL	High-to-low transition time (differential)	20% to 80%, 8H8L test pattern, 16.5 Gbps		28		ps
DDJ	Data dependent jitter, peak-to-peak	PRBS-7 test pattern, JMODE = 0, 12.8 Gbps		8.56		ps
		PRBS-9 test pattern, JMODE = 4, 16.5 Gbps		6.9
		PRBS-9 test pattern, JMODE = 8, 17.16 Gbps		9.28
DCD	Even-odd jitter, peak-to-peak	PRBS-7 test pattern, JMODE = 0, 12.8 Gbps		0.2		ps
		PRBS-9 test pattern, JMODE = 4, 16.5 Gbps		0.01
		PRBS-9 test pattern, JMODE = 8, 17.16 Gbps		0.05
EBUJ	Effective bounded uncorrelated jitter, peak-to-peak	PRBS-7 test pattern, JMODE = 0, 12.8 Gbps		1.63		ps
		PRBS-9 test pattern, JMODE = 4, 16.5 Gbps		0.85
		PRBS-9 test pattern, JMODE = 8, 17.16 Gbps		3.12
RJ	Unbounded random jitter, RMS	8H8L test pattern, JMODE = 0, 12.8 Gbps		0.88		ps
		8H8L test pattern, JMODE = 4, 16.5 Gbps		0.72
		8H8L test pattern, JMODE = 8, 17.16 Gbps		1
TJ	Total jitter, peak-to-peak, with unbounded random jitter portion defined with respect to a BER = 1e-15 (Q = 7.94)	PRBS-7 test pattern, JMODE = 0, 12.8 Gbps		21.35		ps
		PRBS-9 test pattern, JMODE = 4, 16.5 Gbps		18.01
		PRBS-9 test pattern, JMODE = 8, 17.16 Gbps		23.78
ADC CORE LATENCY
t_ADC	Deterministic delay from the CLK± edge that samples the reference sample to the CLK± edge that samples SYSREF going high⁽¹⁾	JMODE = 0		–2		t_CLK cycles
		JMODE = 1		1
		JMODE = 2		–1
		JMODE = 3		–1
		JMODE = 4		–1
		JMODE = 5		–1
		JMODE = 6		1
		JMODE = 7		–1
		JMODE = 8		–1
		JMODE = 9		–1
		JMODE = 10		–2
		JMODE = 11		–2
		JMODE = 12		–1
		JMODE = 13		2
		JMODE = 14		–2
		JMODE = 15		–2
JESD204C AND SERIALIZER LATENCY
t_TX	Delay from the CLK± rising edge that samples SYSREF high to the first bit of the multiframe (8B/10B encoding) or extended multiblock (64B/66B encoding) on the JESD204C serial output lane corresponding to the reference sample of t_ADC⁽²⁾	JMODE = 0	49.8		56.6	t_CLK cycles
		JMODE = 1	45.5		52.8
		JMODE = 2	45.5		52.8
		JMODE = 3	44.3		50.5
		JMODE = 4	42.1		48
		JMODE = 5	42.1		48
		JMODE = 6	53.3		60.2
		JMODE = 7	53.3		60.2
		JMODE = 8	47.1		54.2
		JMODE = 9	58.4		65
		JMODE = 10	56.2		63.1
		JMODE = 11	66.3		74.5
		JMODE = 12	87.2		94.8
		JMODE = 13	72.9		83.9
		JMODE = 14	61.7		68.1
		JMODE = 15	94		103.3
SERIAL PROGRAMMING INTERFACE (SDO)
t_(OZD)	Delay from the falling edge of the 16th SCLK cycle during read operation for SDO transition from tri-state to valid data		1			ns
t_(ODZ)	Delay from the SCS rising edge for SDO transition from valid data to tri-state				10	ns
t_(OD)	Delay from the falling edge of SCLK during read operation to SDO valid		1		10	ns

(1) t_ADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high capture point, in which case the total latency is smaller than the delay given by t_TX.

(2) The values given for t_TX include deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will vary. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe clock (LMFC) cycle.