ZHCSNM2A December 2021 – April 2022 ADC128S102-SEP
PRODUCTION DATA
| MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| CONVERSION CYCLE | ||||||
| fSCLK | Serial clock frequency | VA = VD = 2.7 V to 5.25 V | 0.8 | 16 | MHz | |
| Serial clock duty cycle | VA = VD = 2.7 V to 5.25 V | 40% | 60% | |||
| fS | Sample rate in continuous mode | VA = VD = 2.7 V to 5.25 V | 50 | kSPS | ||
| tCONVERT | Conversion (hold) time | VA = VD = 2.7 V to 5.25 V | 13 | SCLK | ||
| tACQ | Acquisition (track) time | VA = VD = 2.7 V to 5.25 V | 3 | SCLK | ||
| tCYCLE | Throughput time | (tCONV + tACQ) at VA = VD = 2.7 V to 5.25 V |
16 | SCLK | ||
| SPI INTERFACE TIMINGS | ||||||
| tCSH | CS hold time after SCLK rising edge | 10 | 2 | ns | ||
| tCSS | CS setup time prior to SCLK rising edge | 10 | 4.5 | ns | ||
| tDS | DIN setup time prior to SCLK rising edge | 10 | ns | |||
| tDH | DIN hold time after SCLK rising edge | 10 | ns | |||
| tCH | SCLK high time | 0.4 x tSCLK | ns | |||
| tCL | SCLK low time | 0.4 x tSCLK | ns | |||