ZHCSON8A July 2021 – October 2024 ADC09DJ800-Q1 , ADC09QJ800-Q1 , ADC09SJ800-Q1
PRODUCTION DATA
Two LVDS clock outputs are provided to simplify system clocking architectures. These outputs are shown in Figure 6-5. The first LVDS clock output is PLLREFO±. PLLREFO± repeats the PLL reference clock directly from the selected reference clock input (CLK± or SE_CLK) as determined by PLLREF_SE. The PLLREFO± output is automatically enabled when the C-PLL is enabled, but can be disabled by setting PLLREFO_EN to 0. This output is only available when the PLL_EN pin is set high and when PD is set low. Setting PD high disables this output; and therefore, PD should not be used if PLLREFO± is necessary for system operation. Example use cases for PLLREFO± include driving the digital core fabric of an FPGA or ASIC or it can be daisy chained to the CLK± input pins of an additional device to provide the PLL reference clock for the second device. The PLLREFO± outputs can be daisy chained to the CLK± inputs of as many ADC09xJ800-Q1 devices as required by the system. Note that SYSREF must be provided from a separate clock source (clock chip, FPGA, ASIC, etc) and setup and hold times must be met at each device relative to the reference clock input in order to achieve deterministic latency and synchronization.
The second LVDS clock output is TRIGOUT±. This output can come from either the TMSTP± input (as a timestamp or trigger output) or from the JESD204C SerDes PLL (S-PLL). This clock output is not available at device startup and must be enabled through the SPI interface. The S-PLL can be divided by the RX_DIV divider and output from the TRIGOUT± pins as a reference clock for FPGA or ASIC transceiver block. Enable the TRIGOUT± output and set the TRIGOUT± operating mode (including RX_DIV divider) through the TRIGOUT_CTRL register. The TRIGOUT± clock output frequency can be calculated by Equation 6 when the S-PLL is chosen as the TRIGOUT± source.
where