OBSSk Spice MacroV1.00 98/01/15%TINA Device Editor 9.3.200.277 SF-TI Copyright 1997 DesignSoft, Inc. R2LMH7322LMH7322SC:\Users\a0227287\AppData\Local\Temp\DesignSoft\{Tina9-TI-01072020-103954}\LMH7322SCK#LMH7322Label¨ÿÈÿX8°ÿÈÿP8`@´ÿ¹ÿ d*LEH)+V(LATCH_BAR ¨ÿøÿ @d*IN--V(LATCH_BAR) ¨ÿèÿ @d*LEBAR*42 + .9^(. ¨ÿ @d*QBARUPPLY_BUFFER ¨ÿ( @d*Q25x)*42 + .9^(. ¨ÿ @d*IN+>V(2)-1M),V(V ¨ÿØÿ @d*RHYS Xðÿ @d*RHREFD`;Þ Xàÿ @d*VCCI X @d*VEE>=V(2)),V(VSS X @d*VCCON,COM),V(VCC X @f°ÿÈÿP8€ÿÿg"LMH7322Arialåÿøÿ333333ó?€Ö\––Øvå@Ö\––Øvå@+* source LMH7322N*****************************************************************************J* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedH** or implied, with respect to this model, including the warranties of F** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality)** and performance is with the customer.N******************************************************************************D* This model is subject to change without notice. Texas Instruments:* Incorporated is not responsible for updating this model*N******************************************************************************'** Released by: Texas Instruments Inc.* Part: LMH7322* Date: 04/30/2020* Model Type: All In One* Simulator: PSPICE !* Simulator Version: 17.2.0.p001* EVM Order Number: N/A * EVM Users Guide: N/A $* Datasheet: SNOSAU8I - MARCH 2013 * Model Version: 1.0*N****************************************************************************** * Updates:** Version 1.0 : Release to Web&* 2.0 : Improving Convergence*N***************************************************************************** * Notes:)* The following parameters are modeled: 3* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhys, LE, LEBARs* If the input pins, latch pins or supply rail goes beyond the abs max limits, the output will float at mid supplyW* If both inputs go beyond the commmon mode limit, the output will float at mid supply\* If one input goes beyond the commmon mode limit, the output will reflect the input states+* Latch setup/hold/delay times not modeled** Modeled based off of 12V EC table specsN*****************************************************************************C.SUBCKT LMH7322 IN+ IN- LE LEBAR Q QBAR RHREF RHYS VCCI VCCO VEE CX_U2 IN+ IN- LE LEBAR Q QBAR RHREF RHYS VCCI VCCO VEE SCHEMATIC1 .ENDS G.SUBCKT SCHEMATIC1 IN+ IN- LE LE_BAR Q QBAR RHREF RHYS VCCI VCCO VEE V_V15 N740893 0 .4-X_U27 LE LE_BAR LATCH_EN VCCI VEE VinRange .X_U30 LE LE_BAR VCCO VEE N768198 OUT1 Latch #R_R16 N781870 0 1 TC=0,0 #R_R18 N782479 0 1 TC=0,0 4X_U28 VCCX_EN LATCH_EN EN VCCI VEE ANDGATE8X_U21 VCCI_EN VCCO_EN VCCX_EN VCCI VEE ANDGATE)E_E3 N741601 0 N741179 N741241 1I_I2 VCCO 0 DC 16.3m )R_R13 N768397 N768401 1 TC=0,0 =X_U22 VCCO N741241 OUT_VCM PARAMS: HIGH=0.8 LOW=1.4#E_E6 N741641 0 N768401 0 1"R_R12 0 RHREF 1k TC=0,0 I_I3 0 RHYS DC 1 X_U17 N741235 OUT Delay C_C2 0 Q 1p TC=0,0 3X_F1 N781861 N781870 IN- N782060 SCHEMATIC1_F1 7X_U19 EN IN_EN VCCI VEE OUT2 N768965 OUTPUT_EN$C_C1 0 N768401 1p TC=0,0 1X_U12 IN+_B IN-_B IN_CM_EN VCCI VEE VinCMRange #R_R17 N782166 0 1 TC=0,0 *X_U31 SUB N782393 N781861 IB_LUT $R_R2 RHYS RHREF 1k TC=0,0 I_I1 VCCI 0 DC 6.5m =X_U23 VCCO N741709 OUT_VCM PARAMS: HIGH=0.8 LOW=1.4!C_C3 0 QBAR 1p TC=0,0 %E_E1 N741179 0 N740951 OUT 19X_U20 IN_CM_EN IN_ABS_EN IN_EN VCCI VEE ANDGATEV_V12 N740951 0 .41X_U14 VCCO_EN VCCI_B VCCO_B VEE_B SupplyEnable 3X_F2 N782166 N782393 N782479 IN+ SCHEMATIC1_F2 @X_U8 IN+_B IN-_B COMP_OUT N740893 0 N741641 HPA_COMPHYS/X_U10 IN+ IN- IN+_B IN-_B INPUT_BUFFER#R_R19 N782060 0 1 TC=0,0 =X_U3 VCCI VCCO VEE VCCI_B VCCO_B VEE_B SUPPLY_BUFFER1X_U15 VCCI_EN VCCI_B VCCI_B VEE_B SupplyEnable E_E7 SUB 0 IN+ IN- 1.X_U29 LE LE_BAR VCCO VEE N741601 OUT2 Latch 7X_U18 EN IN_EN VCCI VEE OUT1 N768607 OUTPUT_EN$E_E2 N741235 0 COMP_OUT 0 1#R_R14 N768607 Q 1 TC=0,0 0X_U13 IN+_B IN-_B IN_ABS_EN VCCI VEE VinRange $X_U26 RHYS N768397 HYS_RES &R_R15 N768965 QBAR 1 TC=0,0 %E_E5 N768198 0 OUT N741709 1.ENDS (.SUBCKT SupplyEnable EN VCCI VCCX VEE 3X_U15 N683042 0 N683152 VCCI VEE VCC_Range3X_U13 VCCX VEE N683042 VCCI VEE DIFFERENCE3X_U16 N683018 N683152 EN VCCI VEE ANDGATEV_V1 N683000 0 13.28X_U5 N683000 N683042 N683018 VCCI VEE VCC_RANGE.ENDS ..SUBCKT VinCMRange INN INP INRANGE VCCI VEE 5X_U24 N41749 N41859 N41837 VCCI VEE ANDGATE2X_U5 N41693 INP N41749 VCCI VEE VCC_RANGE3X_U23 INN N42361 N42271 VCCI VEE VCC_RANGE4X_U18 N41837 N42077 INRANGE VCCI VEE ORGATE3X_U22 N42121 INN N42177 VCCI VEE VCC_RANGE5X_U25 N42177 N42271 N42077 VCCI VEE ANDGATEV_V11 N41947 VEE -.2V_V4 N42361 VEE -.2V_V12 N41693 VCCI -1.5V_V3 N42121 VCCI -1.53X_U21 INP N41947 N41859 VCCI VEE VCC_RANGE.ENDS .SUBCKT Delay VIN VOUT #E_E2 N669175 0 N668473 0 1.T_T1 N669175 0 VOUT 0 Z0=50 TD=596p !R_R14 0 VOUT 50 TC=0,0 $C_C6 0 N668473 1p TC=0,0 (R_R13 VIN N668473 38.4 TC=0,0 .ENDS ,.SUBCKT Latch LE LE_BAR VCCO VEE VIN VOUT AE_U1 VOUT 0 VALUE {LIMIT(V(N685574,VOUT)*1e5,-15V,+15V)}%C_C1 0 N685574 10n TC=0,0 6X_U2_U30_S1 N685508 0 VIN N685574 Latch_U2_U30_S1 3X_U4 VCCO VEE LE LE_BAR N685508 SWITCH_EN .ENDS ,.SUBCKT VinRange INN INP INRANGE VCCI VEE 8X_U23 N735335 N735433 N735261 VCCI VEE ANDGATE8X_U16 N735009 N735101 N735091 VCCI VEE ANDGATEV_V2 N735135 VCCI .2V_V4 N735499 VEE -.25X_U22 INN N735499 N735433 VCCI VEE VCC_RANGE4X_U5 N734993 INP N735009 VCCI VEE VCC_RANGE5X_U20 N735135 INN N735101 VCCI VEE VCC_RANGEV_V3 N735345 VEE -.25X_U21 INP N735345 N735335 VCCI VEE VCC_RANGE8X_U24 N735091 N735261 INRANGE VCCI VEE ANDGATEV_V1 N734993 VCCI .2.ENDS .subckt SCHEMATIC1_F1 1 2 3 4 F_F1 3 4 VF_F1 1VF_F1 1 2 0V.ends SCHEMATIC1_F1 .subckt SCHEMATIC1_F2 1 2 3 4 F_F2 3 4 VF_F2 1VF_F2 1 2 0V.ends SCHEMATIC1_F2".subckt Latch_U2_U30_S1 1 2 3 4 S_S1 3 4 1 2 _S1RS_S1 1 2 1G9.MODEL _S1 VSWITCH Roff=1E11 Ron=1n Voff=0 Von=1.ends Latch_U2_U30_S1.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$$.SUBCKT Difference 1 2 OUT VDD VSS !EOUT OUT 0 VALUE = { V(1)- V(2)} R1 OUT 2 1 C1 2 0 1e-12.ENDS*$1.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS/EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }DEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }R1 OUT OUT_OUT 1C1 OUT_OUT 0 100e-12.ENDS*$.SUBCKT HYS_RES 1 OUT HERHYS RHYS 0 VALUE = {((1000*(V(1)-1000))/(1000*1 - (V(1)-1000)))/1000}wEHYS HYS 0 VALUE = {LIMIT ((.4**(.25*V(RHYS))*42 + .9**(.3*(V(RHYS)-4))*2 + .5**(.07*(V(RHYS)+3))*8)*.001, 51.1858,0)}EEOUT OUT 0 VALUE = {IF ((V(1)<= 2000 & V(1) >= 1999.9) , 0 ,V(HYS))}*$I*.4**(.25*V(RHYS))*42 + .9**(.3*(V(RHYS)-4))*2 + .5**(.07*(V(RHYS)+3))*81*.4^(.25x)*42 + .9^(.3(x-4))*2 + .5^(.07(x+3))*8.ENDS!.SUBCKT INPUT_BUFFER 1 2 INP INNEINP_NEW INP 0 VALUE = {V(1)}EINN_NEW INN 0 VALUE = {V(2)}.ENDS*$.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS*$'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSSeEOUT OUT 0 VALUE = { IF( ((V(1) < (V(VDD)+V(VSS))/2 ) & (V(2) < (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS*$+.SUBCKT SUPPLY_BUFFER 1 2 3 VCCI VCCO VEE EVCCI_NEW VCCI 0 VALUE = {V(1)} EVCCO_NEW VCCO 0 VALUE = {V(2)}EVEE_NEW VEE 0 VALUE = {V(3)} C1 3 0 1e-12.ENDS*$).SUBCKT SWITCH_EN 1 2 LATCH LATCH_BAR EN/EDIFF DIFF 0 VALUE = {V(LATCH) - V(LATCH_BAR)}/ECM CM 0 VALUE = {(V(LATCH) + V(LATCH_BAR))/2}`EOUT EN 0 VALUE = { IF( (( V(DIFF) > 0& V(CM) > (V(2) + 1.4)) & (V(CM)< (V(1) - .8))), 0, 1 ) }Y*EOUT EN 0 VALUE = { IF( ((V(LATCH) > (V(2) + 1.4)) & (V(LATCH)< (V(1) - .8))), 0, 1 ) }.ENDS*$#.SUBCKT VCC_Range 1 2 OUT VDD VSS BEOUT OUT 0 VALUE = { IF( ( V(1) > V(2) - 1m ), V(VDD), V(VSS) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS >EOUT OUT 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$..SUBCKT OUTPUT_EN VS_EN IN_EN VCCI VEE IN OUT0EVMID VMID 0 VALUE = { ( V(VCCI) + V(VEE) )/2 }^EOUT OUT 0 VALUE = { IF( ((V(VS_EN)> V(VMID) ) & (V(IN_EN) > (V(VMID) ))), V(IN), V(VMID) ) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$.SUBCKT OUT_VCM VCCO OUT + params: + high = 1.1 + low = 1.5@EVMID VMID 0 VALUE = { (( V(VCCO) - high) + (V(VCCO) - low))/2}'EOUT OUT 0 VALUE = { -1*(V(VMID)-.4) } R1 OUT 2 1 C1 2 0 1e-12.ENDS*$.subckt VLIM IN COM VO VCCO + params: + high = 1.1 + low = 1.5CGVO COM VO Value = {LIMIT(V(IN,COM),V(VCCO) - high,V(VCCO) - low)} RVO COM VO 1.ENDS.subckt IB_LUT IN IOUT+ IOUT- + params: + low = -5e-6 + a = -1.5+ b = -1.5001 + c = -1 + d = -1.001 + e = -.2 + f = -.2001 + g = 0 + n = .0001 + h = .2 + i = .2001+ j = 1 + k = 1.001 + l = 1.5 + m = 1.5001:E7 e3n 0 VALUE = {(8*10**(-8)*(-V(IN)+.34)**23.07)*10e-5}.E8 l4n 0 VALUE = {0.0028542*-V(IN) -0.004271}8E3 e3 0 VALUE = {(8*10**(-8)*(V(IN)+.34)**23.07)*10e-5},E4 l4 0 VALUE = {0.0028542*V(IN) -0.004271}(E1 l1 0 VALUE = {12.5e-6*V(IN) -2.5e-6}*E5 l1n 0 VALUE = {-12.5e-6*V(IN) -2.5e-6}AE7n x3n 0 VALUE = {(8*10**(-8)*(-V(IN)+.34)**23.07)*-10e-5-5e-6}6E8n i4n 0 VALUE = {0.0028542*V(IN) + 0.004271 - 5e-6}?E3n x3 0 VALUE = {(8*10**(-8)*(V(IN)+.34)**23.07)*-10e-5-5e-6}6E4n i4 0 VALUE = {-0.0028542*V(IN) + 0.004271 - 5e-6}*E1n i1 0 VALUE = {-12.5e-6*V(IN) -2.5e-6}*E5n i1n 0 VALUE = {12.5e-6*V(IN) -2.5e-6}tEPOS POS 0 VALUE = {IF(V(IN)>g&V(IN)h&V(IN)j&V(IN)l,V(l4),0))))} |G1 IOUT+ 0 VALUE = {IF(V(IN)b&V(IN)d&V(IN)f&V(IN)g&V(IN)h&V(IN)j&V(IN)l,V(i4),0))))} ~G2 IOUT- 0 VALUE = {IF(V(IN)b&V(IN)d&V(IN)f&V(IN)