OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA 9.3.200.277 SF-TIB(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved._ $Circuit$?[All] minx8=25.8 maxx8=29.85 divsx8=13 scalex8=0 minx1=1E-9 maxx1=1.1E-8 divsx1=2 scalex1=0miny1=1.033503608maxy1=1.366472366 divsy1=1 scaley1=0[Vin] miny1=25 maxy1=31 divsy1=3 scaley1=0 c@c ArialDo not float LE_HYST pin. !TINA will ground floating nodes.)Place 1G resistor to VEE for "floating".Symbol????333333??@ ArialLVDS Recovery - TLV3605Symbol????333333??:@: Arial&* Model Notes:*>* Model emulates typical room temperature performace at 3.3V.** Modeled parameters:$* Supply voltage range (see below)7* Supply current - both Enabled and Disabled current.8* Input Bias Currents - both inputs and shutdown pins.&* Typical Offset Voltage (see below)* Propagation Delay (fixed) * Output Latch and Latch Delay * Shutdown5* Hysteresis voltage vs LE/HYST voltage (see below)#* Input Voltage Range (see below)*E* INCORRECT INPUT CONDITIONS: If an error condition occurs, such as Y* incorrect supply votlages or exceeding input votlage range, both outputs will drop to N* VEE (same as shutdown condition) and supply current will drop to 1uA. Input/* votlage range is referenced to VEE and VCCI.*J* LE_HYST pin: This pin can accept a resistor or external votlage to set F* the hysteresis votlage up to 60mV. Valid hysteresis input range is M* 0.8V to 1.25V (see datasheet). Some simulators will not accept a floating K* pin, so connect a 1G resistor from LE_HYST to VEE to set 0mV hysteresis.I* Hysteresis votlage is 0mV when LE_HYST > 1.25V. Output is latched when-* LE_HYST is 0V to 0.4V (referenced to VEE).*G* SHUTDOWN: Each output is lightly pulled-down to VEE by internal 10M L* resistors to prevent floating node or convergence errors during shutdown.9* These resistors are not required on the actual device.*P* OFFSET VOLTAGE: Offset voltage can be adjusted in the macro with device V_VOS*@* VEE: In some simualtors (Cadence), it may be necessary to addO* a 1u resistor in series with VEE to ciruit GND (0 node) for proper operation(* (to break up the VEE and zero nodes).*:*There is about a 1.2ns start-up time for the simulation.Symbol????333333??;xxxxT_0FFAAE6020210506111014?T_0FFAB22020210506111014;T_0FFAB9A020210506111014;((((T_0FFABD6020210506111014?(X((XT_0FFAC12020210506111014?xxxT_0FFAC4E020210506111014;T_0FFAC8A020210506111014;T_0FFACC6020210506111014CT_0FFAD02020210506111014;T_0FFAD3E020210506111014;(0(((0((T_0FFAD7A020210506111014;xxT_0FFADB6020210506111014;xxT_0FFADF2020210506111014;HHHHT_0FFAE2E020210506111014;((((T_0FFAEE2020210506111014;h`h`T_0FF236E020210506111014;8x88x8T_0FF2C56020210506111014;xHx@xHx@T_1169761020210506111014?(8((8T_0354FBE020210506111014;8888T_03513D1020210506111014?H8HH8T_0350E0A020210506111014;T_035B647020210506111016;T_035B683020210506111016;XXXXT_035ABB8020210506111018;XXT_035AB7C020210506111018 BRLT_0D50627020210330123755R_AX600_W200 (R)Y@@?Y@:B;8 U1 T_048FD6F020210401123012 TLV3605TLV3605SC:\Users\a0411595\AppData\Local\Temp\DesignSoft\{Tina9-TI-04232020-103819}\TLV3605SCK#TLV3605LabelD7B5p8 d*IN+HYST  @d*IN-N! @d*VCCI=V(2)),V(VDD @d*VCCOTDOWN)>(V(VS  @d*VEE)<=0.4,0,5)V 0 @d*OUTPUPPLY_BUFFER@@ @d*OUTNUPPLY_BUFFERA@ @d*SHDN  @d*LE_HYST2)),V(VSS0 @gVCCIArialm۶m?gSHDNArialm۶m?gOUTPArialm۶m?gOUTNArialm۶m?gVEEArialm۶m?gVCCOArialm۶m?g"LE/HYSTArial$I$I?e1#dde0$ddh A4a4heddedde(ddg+INArialm۶m?g-INArial m۶m?+@+@k *TLV3605N*****************************************************************************M* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved. N*****************************************************************************H** This model is designed as an aid for customers of Texas Instruments.K** TI and its licensors and suppliers make no warranties, either expressedG** or implied, with respect to this model, including the warranties ofF** merchantability or fitness for a particular purpose. The model isK** provided solely on an "as is" basis. The entire risk as to its quality(** and performance is with the customerN******************************************************************************D* This model is subject to change without notice. Texas Instruments;* Incorporated is not responsible for updating this model.*N******************************************************************************&* Released by: Texas Instruments Inc.* Part: TLV3605* Date: 04/01/2021* Model Type: TRANSIENT* Simulator: TINA-TI'* Simulator Version: 9.3.200.277 SF-TID* Datasheet: SNOSDA2C AUGUST 2020 REVISED MARCH 2021 (3605 preprod)** Model Version: 1.00*N******************************************************************************* Model Notes:*>* Model emulates typical room temperature performace at 3.3V.** Modeled parameters:$* Supply voltage range (see below)7* Supply current - both Enabled and Disabled current.8* Input Bias Currents - both inputs and shutdown pins.&* Typical Offset Voltage (see below)* Propagation Delay (fixed) * Output Latch and Latch Delay * Shutdown5* Hysteresis voltage vs LE/HYST voltage (see below)#* Input Votlage Range (see below)*O* Incorrect Input Conditions: If an error condition occurs, such as incorrect O* supply votlages or exceeding input votlage range, both outputs will drop to N* VEE (same as shutdown condition) and supply current will drop to 1uA. Input/* votlage range is referenced to VEE and VCCI.*J* LE_HYST pin: This pin can accept a resistor or external votlage to set F* the hysteresis votlage up to 60mV. Valid hysteresis input range is L* 0.8V to 1.25V (see datasheet. Some simulators will not accept a floating K* pin, so connect a 1G resistor from LE_HYST to VEE to set 0mV hysteresis.I* Hysteresis votlage is 0mV when LE_HYST > 1.25V. Output is latched when-* LE_HYST is 0V to 0.4V (referenced to VEE).*G* SHUTDOWN: Each output is lightly pulled-down to VEE by internal 10M L* resistors to prevent floating node or convergence errors during shutdown.9* These resistors are not required on the actual device.*I* OFFSET VOLTAGE: Offset voltage can be adjusted below with device V_VOS*@* VEE: In some simualtors (Cadence), it may be necessary to addO* a 1u resistor in series with VEE to ciruit GND (0 node) for proper operation(* (to break up the VEE and zero nodes).*=.SUBCKT TLV3605 IN+ IN- VCCI VCCO VEE OUTP OUTN SHDN LE_HYST*Offset Voltage below&V_VOS N833987 IN+_BUFFER 500uGX_U4 IN-_BUFFER IN+_BUFFER N00790 VCCI_BUFFER VEE_BUFFER INPUT_RANGE 2X_U1 VCCO V+_BUFFER VEE V-_BUFFER SUPPLY_BUFFER GX_U11 SHDN VLOGIC 0 SHUTDOWN_IQ_CONTROL VCCI_BUFFER VEE_BUFFER+ SHUTDOWNCURRENT V_V8 VLOGIC 0 5EX_U9 N833987 IN-_BUFFER N811399 VLOGIC 0 HYSTERESIS VLOGIC 0+ HPA_COMPHYSPX_U10 N836302 N00790 OUTN OUTP SHUTDOWN_IQ_CONTROL N822051 VLOGIC OUTPUT_STAGE + >X_U13 LE_HYST VEE 0 VLOGIC N840164 HYSTERESIS LE_HYST2X_U3 IN+ IN+_BUFFER IN- IN-_BUFFER INPUT_BUFFER /X_U2 N00799 V+_BUFFER V-_BUFFER SUPPLY_CHECK $X_U12 LATCH N836302 N840210 LATCH *X_PROP_DELAY N811399 N840210 PROP_DELAY *X_LATCH_DEALY N840164 LATCH LATCH_DELAY 8X_U14 VCCI_ENABLE VCCI_BUFFER VEE_BUFFER SUPPLY_CHECK :X_U16 N00799 VCCI_ENABLE N822051 VLOGIC 0 ORGATE >X_U17 VCCI VEE VCCI_BUFFER VEE_BUFFER SUPPLY_BUFFER1 FX_Supply_Currents SHUTDOWN_IQ_CONTROL VCCI VCCO VEE Supply_Currents $I_I1 SHDN N8422771 DC 1uA $I_IBP N843036 VEE DC -1uA $I_IBN N842716 VEE DC -1uA %R_RIN IN- N842716 1 TC=0,0 %R_RIP IN+ N843036 1 TC=0,0 'R_RISD VEE N8422771 1 TC=0,0 .ENDS 4.SUBCKT Supply_Currents SHUTDOWN_IN VCCI VCCO VEE :X_U1 VCCO VEE SHUTDOWN_IN N831741 N831734 IS_SET:X_U2 VCCI VEE SHUTDOWN_IN N831755 N831748 IS_SETV_V1 N831734 0 100uV_V2 N831741 0 5.2mV_V3 N831748 0 1.5mV_V4 N831755 0 7.5m.ENDS .SUBCKT LATCH_DELAY VIN VOUT E_E1 N05708 0 VIN 0 2)R_RT1 N056220 N05708 50 TC=0,0 ,T_T1 N056220 0 VOUT 0 Z0=50 TD=4n !R_RT2 0 VOUT 50 TC=0,0 .ENDS .SUBCKT PROP_DELAY VIN VOUT !R_RT2 0 VOUT 50 TC=0,0 E_E1 N05043 0 VIN 0 2.T_T1 N037060 0 VOUT 0 Z0=50 TD=600p )R_RT1 N037060 N05043 50 TC=0,0 .ENDS .SUBCKT LATCH LATCH OUT VIN =X_U6 LATCH N02206 N02306 N02592 VLOGIC 0 DIGLEVSHIFT0X_U2 N02184 N02212 OUT VLOGIC 0 NORGATEV_V7 N02306 0 50X_U5 N02206 VIN N02696 VLOGIC 0 ANDGATE*X_U1 VIN N02178 VLOGIC 0 INVERTER0X_U3 OUT N02696 N02212 VLOGIC 0 NORGATE3X_U4 N02178 N02206 N02184 VLOGIC 0 ANDGATEV_V1 VLOGIC 0 5V_V8 N02592 0 0.ENDS ..SUBCKT SUPPLY_CHECK EN V+_BUFFER V-_BUFFER DX_U17 N22961 0 N23037 EN V+_BUFFER V-_BUFFER ENABLE_TLV7021V_V5 N23037 0 5V_V4 N23097 0 2.5V_V1 N22785 0 5.5@X_U16 N22797 N22971 N22961 V+_BUFFER V-_BUFFER ANDGATE9X_U19 N22815 N23097 N22971 V+_BUFFER 0 VCC_RANGE4X_U18 V+_BUFFER V-_BUFFER N22815 DIFFERENCE8X_U5 N22785 N22815 N22797 V+_BUFFER 0 VCC_RANGE.ENDS 1.SUBCKT INPUT_BUFFER IN+ IN+_BUFF IN- IN-_BUFF 7X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 .ENDS J.SUBCKT OUTPUT_STAGE IN INRANGE OUTN OUTP SHUTDOWN SUPPLY_ENABLE VLOGIC $C_C2 0 N801294 1p TC=0,0 &R_RPDP 0 OUTP 100MEG TC=0,0 $C_C1 0 N801028 1p TC=0,0 =X_U4 VLOGIC 0 SHUTDOWN 0 SHUTDOWN_OUT SHUTDOWNOUTPUT:X_S17 OUTPUT_SHUTDOWN 0 OUTN N801294 OUTPUT_STAGE_S17 &R_RPDN 0 OUTN 100MEG TC=0,0 EX_U3 OUTOFRANGE SHUTDOWN_OUT OUTPUT_SHUTDOWN VLOGIC 0 ORGATE5X_S13 0 CONTROL N800934 N800956 OUTPUT_STAGE_S13 )R_R1 N800956 N801132 1k TC=0,0 5X_S12 0 CONTROL N800960 N801352 OUTPUT_STAGE_S12 >X_U2 INRANGE SUPPLY_ENABLE OUTOFRANGE VLOGIC 0 ORGATE3X_U5 IN SHUTDOWN CONTROL VLOGIC 0 ANDGATE *R_R4 N800956 N801294 0.1 TC=0,0 )R_R2 N801132 N800960 1k TC=0,0 V_V9 N800810 0 0*R_R3 N800960 N801028 0.1 TC=0,0 5X_S11 CONTROL 0 N800934 N800960 OUTPUT_STAGE_S11 :X_S16 OUTPUT_SHUTDOWN 0 N801028 OUTP OUTPUT_STAGE_S16 V_V10 N801132 0 1.25X_S14 CONTROL 0 N800956 N801352 OUTPUT_STAGE_S14 !I_I8 N801352 0 DC 3.5m 'I_I7 N800810 N800934 DC 3.5m .ENDS 2.SUBCKT SUPPLY_BUFFER V+ V+_BUFFER V- V-_BUFFER 7X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 .ENDS :.SUBCKT INPUT_RANGE INN INP INRANGE V+_BUFFER V-_BUFFER "V_V4 N29318 V-_BUFFER -.3LX_U20 N28732 N28962 0 N29032 INRANGE V+_BUFFER V-_BUFFER ORGATE1701>X_U18 N28652 N28742 N28732 V+_BUFFER V-_BUFFER ORGATE@X_U1 N28632 INP N28652 V+_BUFFER V-_BUFFER VINRANGE_393@X_U3 INP N29122 N29100 V+_BUFFER V-_BUFFER VINRANGE_393"V_V2 N28834 V+_BUFFER 0.3AX_U17 INN N29318 N29208 V+_BUFFER V-_BUFFER VINRANGE_393V_V5 N29032 0 5"V_V1 N28632 V+_BUFFER 0.3>X_U19 N29100 N29208 N28962 V+_BUFFER V-_BUFFER ORGATE@X_U2 N28834 INN N28742 V+_BUFFER V-_BUFFER VINRANGE_393"V_V3 N29122 V-_BUFFER -.3.ENDS#.subckt OUTPUT_STAGE_S17 1 2 3 4 S_S17 3 4 1 2 _S17RS_S17 1 2 1G;.MODEL _S17 VSWITCH Roff=1e12 Ron=1.0 Voff=5 Von=0.ends OUTPUT_STAGE_S17#.subckt OUTPUT_STAGE_S13 1 2 3 4 S_S13 3 4 1 2 _S13RS_S13 1 2 1G?.MODEL _S13 VSWITCH Roff=1e12 Ron=1.0 Voff=-5 Von=-2.5.ends OUTPUT_STAGE_S13#.subckt OUTPUT_STAGE_S12 1 2 3 4 S_S12 3 4 1 2 _S12RS_S12 1 2 1G?.MODEL _S12 VSWITCH Roff=1e12 Ron=1.0 Voff=-5 Von=-2.5.ends OUTPUT_STAGE_S12#.subckt OUTPUT_STAGE_S11 1 2 3 4 S_S11 3 4 1 2 _S11RS_S11 1 2 1G=.MODEL _S11 VSWITCH Roff=1e12 Ron=1.0 Voff=2.5 Von=5.ends OUTPUT_STAGE_S11#.subckt OUTPUT_STAGE_S16 1 2 3 4 S_S16 3 4 1 2 _S16RS_S16 1 2 1G;.MODEL _S16 VSWITCH Roff=1e12 Ron=1.0 Voff=5 Von=0.ends OUTPUT_STAGE_S16#.subckt OUTPUT_STAGE_S14 1 2 3 4 S_S14 3 4 1 2 _S14RS_S14 1 2 1G=.MODEL _S14 VSWITCH Roff=1e12 Ron=1.0 Voff=2.5 Von=5.ends OUTPUT_STAGE_S14 * ADDED LIBS*.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDISEGIS VCC1 VEE VALUE = { IF ( V(DISABLE) > 2.5 , V(VIEN), V(VIDIS) ) }RIS VCC1 VCC 1.ENDS,.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW "EVDD_NEW VDD_NEW 0 VALUE = {V(1)}"EVSS_NEW VSS_NEW 0 VALUE = {V(2)}.ENDS.SUBCKT ORGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) } R1 4 3 1 C1 3 0 1e-12.ENDS8.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUTQEOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}C1 OUT 0 1e-12.ENDS.SUBCKT ANDGATE 1 2 3 VDD VSScE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) } R1 4 3 1 C1 3 0 1e-12.ENDS1.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSSFEOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}R1 OUT OUT2 1C1 OUT 0 1e-12 .ENDS.SUBCKT INVERTER 1 2 VDD VSSAE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) } C1 1 0 1e-12.ENDS .SUBCKT NORGATE 1 2 OUT VDD VSShEOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS8.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEWRE1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) } R1 3 2 1 C1 2 0 1e-12.ENDS;.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT V_VLATCH N00729 V- 1.25)R_RPU N00729 LEHYST 40k TC=0,0 %E_EIN VLE V-_BUF LEHYST V- 1*R_R1 V-_BUF LATCH_OUT 1k TC=0,0 #R_R2 V-_BUF VLE 1k TC=0,0*R_R3 V-_BUF HYST_OUT 1k TC=0,0 AE_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }5E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)+(0.5,0.0636)+(0.55,0.0636)+(0.6,0.0636)+(0.65,0.0636)+(0.7,0.0635)+(0.71,0.0636)+(0.72,0.0635)+(0.73,0.0636)+(0.74,0.0634)+(0.75,0.0635)+(0.76,0.0638)+(0.77,0.0637)+(0.78,0.0637)+(0.79,0.0637)+(0.8,0.0636)+(0.81,0.0636)+(0.82,0.0636)+(0.83,0.0636)+(0.84,0.0425)+(0.85,0.0411)+(0.86,0.0398)+(0.87,0.0386)+(0.88,0.0371)+(0.89,0.0359)+(0.9,0.0347)+(0.91,0.0334)+(0.92,0.032)+(0.93,0.0309)+(0.94,0.0296) +(1,0.0223)+(1.05,0.0164)+(1.1,0.0108)+(1.15,0.0056)+(1.2,0.0007) +(1.25,0).ENDS*.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS /EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }=EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS.SUBCKT Difference 1 2 OUT!EOUT OUT2 0 VALUE = {V(1)- V(2)}R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS#.SUBCKT VCC_Range 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }R1 OUT OUT2 1C1 OUT 0 1e-12.ENDS*$&.SUBCKT VINRANGE_393 1 2 OUT VDD VSS ?EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }R1 OUT2 OUT 1C1 OUT 0 1e-12.ENDS'.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSScEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }.ENDS7.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS V3 V4-EVMID VMID 0 VALUE = { ( V(V3) + V(V4) )/2 }"EVH VH 0 VALUE = { ( V(VHYS)/2) }bEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }FEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), (V(V3)), (V(V4)) ) }R1 OUT OUT_OUT 50C1 OUT_OUT 0 1e-12.ENDS VCCIIN-VEEVCCOIN+OUTNOUTPLE_HYSTSHDNB( Sig_PT_034E894020210401131143 Sgen (VG)333333??eA-q=DBh VCCT_0CF9566020210430091802Battery_9V_V (V)ffffff @BtVout_NT_0CF97F8020210430093553 NOPCB (VF)BtVout_PT_0CF979A020210430093527 NOPCB (VF)Bx Sig_NT_045578D020210504154118 Sgen (VG)333333?eA-q= BR1T_0405E36020210504160153R_AX600_W200 (R)Y@@?Y@ B((R_HYSTT_0F2D5C4020210506110045R_AX600_W200 (R)O"A@?Y@B(  V_Noise_1T_0F2D622020210506110149 Sgen (VG)Q?vH7BBx  V_Noise_2T_0F2D680020210506110526 Sgen (VG)Q?vH7BBsXVin_PT_0F2D6DE020210506111001 NOPCB (VF)BsVin_NT_03659C2020210506111005 NOPCB (VF)Bn`VCCT_0CF9622020210430091814 NOPCB (J)Bn8x VCCT_118AF64020210503092734 NOPCB (J)BfHT_0D50103020210330123413 NOPCB (GND)Bf(0T_0D50451020210330123517 NOPCB (GND)Bf((T_0D5050D020210330123521 NOPCB (GND)BfT_0CF95C4020210430091806 NOPCB (GND)BfxHT_045572F020210504154118 NOPCB (GND)8?h ]@"MbP??ư>'dd?Y@[dddd$@?.A.A.AeAMbP?@@?:0yE>,i)+P>ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname