OBSSCircuit DescriptionV1.1010/02/94 20:07 CET.Component & analysis parameters of a circuit.TINA B(c) Copyright 1993,94,95,96 DesignSoft Inc. All rights reserved.; $Circuit$?>W??ƚJ*O7l(J* EMFp> 8}U HRpMS Sans SerifIP\"MS Sans Serif"I" I"C0PCC"C"I,"A;Int"u,"u,"ntX"it|""Ddv%  '%   TT  Br B LPT  % RpArialpUv[mv("ArialpU":v@""0100000000000000000$&vcv7TI  IpU"pU8:Itzqv6qvdv%  % RpArial 4(f hP0501Arial000|"_itjD|"|itnt"C it"C cv7TI  IpU"U8:ImFϗU%`,ӿ"bMbP?"dv%  % %  % %  % %  % %  % %  % %  % %  % %  % %  % %  % %  % %  % % %  %   +4% %   +4% "}"}&%  6"% L}L}&%  6L}}6L}L}6}LL6% ""%  6"% LL%  6L6LL6LL6% LL&%  6% %  &%    T|P( Br BL\Time (s)  Q% %    TdD_ Br BDLT0.00`% ( LL%  6Laa6aww6w666666  6 % &%    TpE Br BLX10.00uF% ( ""%  6"8868MM6Mcc6cxx6x66666% &%    Tp Br BLX20.00u% ( %  6% L}L}6L% %  &%    T`7G Br B7LTVin 7% %    Tl!sA Br B!sLX-5.00Bs% ( D}D}%  6L}KrKr6LrKgKg6LgK]K]6L]KRKR6LRHGHG6LGK<K<6L<K1K16L1K'K'6L'KK6L% &%    Td&A Br B&LT5.00B% ( DD%  6L% LL6L% %  &%    Td  Br BLTVout !% % ( %  &%    Tl!A Br B!LX-5.20B% ( DD%  6LKK6LKK6LKK6LKK6LHH6LKK6LKK6LKK6LKK6L% &%    Td&A Br B&LT5.20B% ( DD%  6L% % LGLG&%  6LL66}}6"}"}6#G#G6##66}}6}}6G% LL& %  6LL6MM6NN6OO6PP6QQ6RR6TT6VV6YY6]]6aa6ee6gg6ii6jj6ll6mm6oo6qq6rr6ss6tt6vv6xx6yy6{{6||6}}6~~66666666666666666666666666666666666666666666666666666666666666666666666666666666  6  6666666!!6""6""6##6##6##6##6$$6%%6%%6&&6''6((6((6))6**6**6++6,,6--6..6//6226776;;6??6DD6HH6LL6PP6SS6UU6VV6WW6XX6YY6\\6]]6__6``6aa6bb6cc6ee6gg6hh6ii6jj6kk6ll6nn6pp6rr6ss6uu6vv6yy6||6~~666666666666666666666666666666666666666666666666666666666666666666666%  % % % WQ ??ƚJ*O7l)J* EMF Q\ 8}U HRpMS Sans SerifIP\"MS Sans Serif"I" I"C0PCC"C"I,"A;Int"u,"u,"ntX"it|""Ddv%  '%   TT  Br B LPT  % RpArialv""Arial "0D"$H5zqvdi\"" " I\"  o2o"0"6o7voo""0\"i~^Ix"(" I"8:I("dv%  % RpAriale0000Arial0000"_it SD0"|itntt"w=itt"w= D Br B> LP1E % ( EE%  6E __6_oo6oyy6y% & %    TXt  Br Bt LP10 % ( {{%  6{ 666% & %    T`  Br B LT100 % ( %  6 666% & %    TX  Br B LP1k % ( %  6 666% & %    T` + Br B LT10k+ % ( %  6 7767HH6HQQ6Q% & %    TdM i Br BM LT100ki % ( TT%  6T mm6m~~6~6% & %    Td  Br B LT1MEG   % ( %  6 666% & %    Tl  Br B LX10MEG   % ( %  6 666% & %    Tp  Br B LX100MEG   % ( %  6 % EE6E% %  & %    % Rp ArialCvjth6 `"P/jtnt SDnt0s$ "FitSD nt"eitnt! "it" !"*it!  ""'C!  "B 'CT"#/@T"2]@BBPdv%  T Br B LdPhase [deg]=% ( %  % %    Tx?  Br BL\-170.75@% ( AA%  6EDD6EDD6EDD6E% & %    Td(? Br B(LT4.62@% ( AA%  6EDD6EDD6EDD6E% & %    Tp? Br BLX180.00@% ( AA%  6E% % E%  6II6OO6UU6[[6aa6gg6mm6ss6yy6666666666666666666666666666  6&&6,,6226776==6CC6II6OO6UU6[[6aa6gg6mm6ss6yy666666666666666666666%  % % % =\h??ƚJ*O7l(J* EMF=q 8}U HRpMS Sans SerifIP\"MS Sans Serif"I" I"C0PCC"C"I,"A;Int"u,"u,"ntX"it|""Ddv%  '%   TT  Br B LPT  % RpArialpUv[mv("ArialpU":v@""0100000000000000000$&vcv7TI  IpU"pU8:Itzqv6qvdv%  % RpArial 4(f hP0501Arial000|"_itjD|"|itnt"C it"C cv7TI  IpU"U8:ImFϗU%`,ӿ"bMbP?"dv%  % %  % %  % %  % %  % %  % %  % %  % %  % %  % %  % %  % %  % % %  %   +4% %   +4% -}-}&%  6-% a}a}&%  6a}}6a}a}6}aa6% --%  6-% aa%  6a6aa6aa6% aa&%  6% %  &%    T|$Z( Br B$L\Time (s)  [% %    TdYt Br BYLT0.00u% ( aa%  6auu6u66666666% &%    Tp%P Br B%LX10.00uQ% ( --%  6-AA6AVV6Vjj6j666666% &%    Tp Br BLX20.00u% ( %  6% a}a}6a% %  &%    T`7G Br B7LTVin 7% %    Tx!sV Br B!sL\-50.00m Ws% ( Y}Y}%  6a}`r`r6ar`g`g6ag`]`]6a]`R`R6aR^G^G6aG`<`<6a<`1`16a1`'`'6a'``6a% &%    Tp&V Br B&LX50.00m W% ( YY%  6a% aa6a% %  &%    Td  Br BLTVout !% % ( %  &%    Tx!V Br B!L\-60.87m W% ( YY%  6a``6a``6a``6a``6a^^6a``6a``6a``6a``6a% &%    Tp&V Br B&LX61.36m W% ( YY%  6a% % aGaG&%  6aa66}}6-}-}6-G-G6--66}}6}}6G% aa& %  6aa6aa6aa6aa6aa6bb6bb6bb6cc6cc6dd6dd6ee6ff6gg6hh6ii6jj6kk6mm6nn6oo6pp6qq6rr6tt6uu6ww6xx6zz6~~6666666666666666666666666666666666666666666666666666666666666666666666  6  66666!!6%%6))6++6,,6--6--6--6--6--6--6--6--6--6--6..6..6..6..6//6//6//6006006116116116226336446556666886996::6;;6<<6==6>>6??6AA6BB6CC6DD6FF6II6KK6MM6PP6TT6YY6]]6aa6ee6ii6mm6qq6uu6yy6}}6666666666666666666666666666666666666666666666666666666666666666666666%  % % % O9d??ƚJ<,1l 3J<, EMF9 8}U HRpMS Sans SerifIP\"MS Sans Serif"I" I"C0PCC"C"I,"A;Int"u,"u,"ntX"it|""Ddv%  '%   TT  Br B LPT  % RpArialG$"p"h"v|FArialG"o C"|""o010000000000000000018""bv CG8"1x"","0v8pvx"mvQmvDdv%  % RpArial  @9f31188Arial000"_it h"|itnt"pitu "p8""bv CG8"1"","0v8pvx"z@a@H"b?X"dv%  % %  % %  % %  % %  % %  % %  % %  % %  % % %  %   +?% %   +?% ss&%  6s66666666666!!6!3363==6=@@6@[[6[mm6mww6wzz6z6666666% WW&%  6W6% WW%  6WW6WW6WW6WW6WW6WW6WW6WW6W|W|6|WtWt6tWrWr6rW[W[6[WMWM6MWEWE6EWCWC6CW,W,6,WW6WW6% WW%  6WW6% WW&%  6% %  &%    T!t3 Br B!LhFrequency (Hz)   u!% %    TTN V Br BN LP1 W % ( WW%  6Wss6s66% &%    TX  Br B LP10  % ( %  6666% &%    T`  Br B LT100  % ( %  6666% &%    TX  Br B LP1k  % ( %  6!!6!3363==6=% &%    T`7 R Br B7 LT10k R % ( @@%  6@[[6[mm6mww6w% &%    Tdq  Br Bq LT100k  % ( zz%  6z666% &%    Td  Br B LT1MEG   % ( %  6666% &%    Tl  Br B LX10MEG   % ( %  6% WW6W% %  &%    % Rp ArialCvjt6`"P/jtnt hnt0s J"Fith nt"eitnt! "it" !"*it!  ""'C!  "B 'CT"#/@T"2]@JBdv%  Tb Br B L`Zo (ohms)  L% ( %  % %    TpK Br BLX400.00  L% ( NN%  6WSS6WSS6WSS6W% &%    TpK Br BLX633.96  L% ( NN%  6WSS6WSS6WSS6W% &%    Tl#L Br B#LX1.00k  L% ( NN%  6WSS6WS|S|6W|StSt6Wt% &%    Tl#hL{ Br B#hLX1.59k  Lh% ( NrNr%  6WrS[S[6W[SMSM6WMSESE6WE% &%    Tl#9LL Br B#9LX2.52k  L9% ( NCNC%  6WCS,S,6W,SS6WSS6W% &%    Tl# L Br B# LX4.00k  L % ( NN%  6W% % WW&%  6\\6``6ee6jj6nn6ss6xx6||66##6((6//6776AA6LL6YY6ff6uu666666666666666666666  66666$$6((6--6226666;;6@@6DD6II6NN6RR6WW6[[6``6ee6ii6nn6ss6ww6||66666666666666666666666666%  % % % 0H@0H Arial#TLV9302 GWL SPICE simulation modelSymbol????333333??Y@Y ArialLarge Signal Reponse, G=+1Symbol????333333??[K@[K ArialSmall Signal Reponse, G=+1Symbol????333333??L@L ArialOutput Impedance (Zo)Symbol????333333?? @  Arial%Closed Loop Frequency Reponse (G=-1)Symbol????333333??P'@' Arial* TLV9302 - Rev. A)* Created by Paul Goedeke; June 04, 2019B* Created with Green-Williams-Lis Op Amp Macro-model Architecture2* Copyright 2019 by Texas Instruments Corporation7******************************************************$* MACRO-MODEL SIMULATED PARAMETERS:7******************************************************D* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)* UNITY GAIN BANDWIDTH (GBW)9* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)4* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)%* DIFFERENTIAL INPUT IMPEDANCE (Zid)$* COMMON-MODE INPUT IMPEDANCE (Zic)0* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)+* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)1* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)1* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)/* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)%* SHORT-CIRCUIT OUTPUT CURRENT (Isc)* QUIESCENT CURRENT (Iq))* SETTLING TIME VS. CAPACITIVE LOAD (ts)* SLEW RATE (SR)-* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD* LARGE SIGNAL RESPONSE* OVERLOAD RECOVERY TIME (tor)* INPUT BIAS CURRENT (Ib)* INPUT OFFSET CURRENT (Ios)* INPUT OFFSET VOLTAGE (Vos)(* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)C* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm))* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)Symbol????333333??;X0X0T_0666B96020190404154725;T_0666B1E020190404154725;T_0666AA6020190404154725? 0 00T_0666A6A020190404154725? X0` X0X0`T_0666A2E020190404154725;  T_06669F2020190404154725;((T_06669B6020190404154725?T_0644156020190404154725;((((T_064411A020190404154725?T_06440DE020190404154725;T_06440A2020190404154725?88T_0644066020190404154725;T_064402A020190404154725;`X`XT_0643FEE020190404154725;T_0643FB2020190404154725?T_0643F76020190404154725?(8(88T_0643F3A020190404154725;T_0643EFE020190404154725;T_0F64DC5020190404154725;T_0F64E01020190404154725DB` VccT_079BBCC020180215122906 JP100 (V)2@DB(VeeT_079BB6E020180215122906 JP100 (V)2@ BRFT_079BB10020180215122906R_AX600_W200 (R)@@?fffffqY@B VinT_079BAB2020180215122906 JP100 (VG)?@@V BRIT_079BA54020180215122906R_AX600_W200 (R)@@@?fffffqY@BqVosT_079B9F6020180215122906 NOPCB (VF) B(C1T_079BCE6020180215123050CP_CYL300_D700_L1400 (C) dy=@eAY@? BXC2T_0F056F0020180215123248CP_CYL300_D700_L1400 (C) Iz>@eAY@? BC3T_0F05692020180215123248CP_CYL300_D700_L1400 (C) Iz>@eAY@?BrVoutT_0F057AC020180215123307 NOPCB (VF):Bq:(U1T_06582C4020190606141113 TLV9302 :TLV9302SC:\Users\a0225818\AppData\Local\Temp\DesignSoft\{Tina9-TI-11062017-190831}\OPA2990SCK#TLV9302Label#PP(d*IN+8  @d*IN-ptJEz, @d*OUT,  @d*VCCpJ@;  @d*VEE  @h 00g"- Courier New?g"+ Courier New ?g"+ Courier New?%L@%L@* TLV9302 - Rev. A)* Created by Paul Goedeke; June 04, 2019B* Created with Green-Williams-Lis Op Amp Macro-model Architecture2* Copyright 2019 by Texas Instruments Corporation7******************************************************$* MACRO-MODEL SIMULATED PARAMETERS:7******************************************************D* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)* UNITY GAIN BANDWIDTH (GBW)9* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)4* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)%* DIFFERENTIAL INPUT IMPEDANCE (Zid)$* COMMON-MODE INPUT IMPEDANCE (Zic)0* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)+* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)1* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)1* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)/* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)%* SHORT-CIRCUIT OUTPUT CURRENT (Isc)* QUIESCENT CURRENT (Iq))* SETTLING TIME VS. CAPACITIVE LOAD (ts)* SLEW RATE (SR)-* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD* LARGE SIGNAL RESPONSE* OVERLOAD RECOVERY TIME (tor)* INPUT BIAS CURRENT (Ib)* INPUT OFFSET CURRENT (Ios)* INPUT OFFSET VOLTAGE (Vos)(* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)C* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm))* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)7******************************************************$.subckt TLV9302 IN+ IN- VCC VEE OUT7******************************************************* MODEL DEFINITIONS:9.model BB_SW VSWITCH(Ron=50 Roff=1e12 Von=700e-3 Voff=0):.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)?.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3)9.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)&.model R_NOISELESS RES(T_ABS=-273.15)7******************************************************I_OS ESDn MID 5PI_B 23 MID 10PV_GRp 59 MID 400V_GRn 60 MID -400V_ISCp 53 MID 80V_ISCn 54 MID -80V_ORn 38 VCLP -1.9V11 58 37 0V_ORp 36 VCLP 1.9V12 57 35 0V4 50 OUT 0VCM_MIN 80 VEE_B -200MVCM_MAX 81 VCC_B 200MI_Q VCC VEE 120U0XCLAWn MID VIMON VEE_B 21 VCCS_LIM_CLAW-_0XU1 22 23 VOS_DRIFT_0%R61 MID 24 R_NOISELESS 26.7 C16 24 25 13.3N &R58 25 24 R_NOISELESS 100MEG $GVCCS2 25 MID VEE_B MID -375M"R57 MID 25 R_NOISELESS 1 %R56 MID 26 R_NOISELESS 62.5 C15 26 27 6.37N &R55 27 26 R_NOISELESS 100MEG $GVCCS1 27 MID VCC_B MID -160M"R54 MID 27 R_NOISELESS 1 C22 28 MID 30F %R62 MID 28 R_NOISELESS 1MEG GVCCS4 28 MID 29 MID -1U$XVOS_VCM 30 22 VCC VEE VOS_SRC_0Xe_n ESDp 23 VNSE_0+S5 VEE ESDp VEE ESDp S_VSWITCH_1+S4 VEE ESDn VEE ESDn S_VSWITCH_2+S2 ESDn VCC ESDn VCC S_VSWITCH_3+S3 ESDp VCC ESDp VCC S_VSWITCH_4C28 31 MID 1P #R77 32 31 R_NOISELESS 100 C27 33 MID 1P #R76 34 33 R_NOISELESS 100 "R75 MID 35 R_NOISELESS 1 GVCCS8 35 MID 36 MID -1"R74 37 MID R_NOISELESS 1 GVCCS7 37 MID 38 MID -1"R73 39 MID R_NOISELESS 1 )XVCCS_LIM_ZO 40 MID MID 39 VCCS_LIM_ZO_0Xi_nn ESDn MID FEMT_0Xi_np MID 23 FEMT_0C25 29 MID 53.1F %R69 MID 29 R_NOISELESS 1MEG #GVCCS6 29 MID VSENSE MID -1UC20 CLAMP MID 354N (R68 MID CLAMP R_NOISELESS 1MEG *XVCCS_LIM_2 41 MID MID CLAMP VCCS_LIM_2_0%R44 MID 41 R_NOISELESS 1MEG &XVCCS_LIM_1 42 43 MID 41 VCCS_LIM_1_0$R72 40 MID R_NOISELESS 1.3 C26 40 44 1.22P #R71 40 44 R_NOISELESS 10K "R70 44 MID R_NOISELESS 1 GVCCS5 44 MID 45 MID -1C23 46 MID 133P #R67 45 46 R_NOISELESS 10K "R66 45 47 R_NOISELESS 2K "R65 47 MID R_NOISELESS 1 GVCCS3 47 MID 48 MID -9C21 49 48 1.59U &R51 48 MID R_NOISELESS 1.25K #R50 48 49 R_NOISELESS 10K $Rdummy MID 50 R_NOISELESS 40K $Rx 50 39 R_NOISELESS 400K "Rdc 49 MID R_NOISELESS 1 &G_Aol_Zo 49 MID CL_CLAMP 50 -90.1%R49 MID 51 R_NOISELESS 334K C14 51 52 159F &R48 52 51 R_NOISELESS 100MEG $G_adjust 52 MID ESDp MID -23.8M"Rsrc MID 52 R_NOISELESS 1 .XIQp VIMON MID MID VCC VCCS_LIMIT_IQ_0.XIQn MID VIMON VEE MID VCCS_LIMIT_IQ_0C_DIFF ESDp ESDn 3P 1XCL_AMP 53 54 VIMON MID 55 56 CLAMP_AMP_LO_0+SOR_SWp CLAMP 57 CLAMP 57 S_VSWITCH_5+SOR_SWn 58 CLAMP 58 CLAMP S_VSWITCH_6.XGR_AMP 59 60 61 MID 62 63 CLAMP_AMP_HI_0#R39 59 MID R_NOISELESS 1T #R37 60 MID R_NOISELESS 1T &R42 VSENSE 61 R_NOISELESS 1M C19 61 MID 1F "R38 62 MID R_NOISELESS 1 "R36 MID 63 R_NOISELESS 1 "R40 62 64 R_NOISELESS 1M "R41 63 65 R_NOISELESS 1M C17 64 MID 1F C18 MID 65 1F *XGR_SRC 64 65 CLAMP MID VCCS_LIM_GR_0"R21 55 MID R_NOISELESS 1 "R20 MID 56 R_NOISELESS 1 "R29 55 66 R_NOISELESS 1M "R30 56 67 R_NOISELESS 1M C9 66 MID 1F C8 MID 67 1F ,XCL_SRC 66 67 CL_CLAMP MID VCCS_LIM_4_0#R22 53 MID R_NOISELESS 1T #R19 MID 54 R_NOISELESS 1T 0XCLAWp VIMON MID 68 VCC_B VCCS_LIM_CLAW+_0%R12 68 VCC_B R_NOISELESS 1K "R16 68 69 R_NOISELESS 1M %R13 VEE_B 21 R_NOISELESS 1K "R17 70 21 R_NOISELESS 1M C6 70 MID 1F C5 MID 69 1F $G2 VCC_CLP MID 69 MID -1M(R15 VCC_CLP MID R_NOISELESS 1K $G3 VEE_CLP MID 70 MID -1M(R14 MID VEE_CLP R_NOISELESS 1K V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}OGVO- COM VO- VALUE = {IF(V(VIN,COM)V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}OGVO- COM VO- VALUE = {IF(V(VIN,COM)10E-3 | V(OLP,COM)>10E-3),1,0)}.ENDS*6.SUBCKT VCCS_EXT_LIM_0 VIN+ VIN- IOUT- IOUT+ VP+ VP-.PARAM GAIN = 1IG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}.ENDS*IN+IN-VCCVEEOUTBfT_079B998020180215122906 NOPCB (GND)Bf8T_079B93A020180215122906 NOPCB (GND)BfT_079B8DC020180215122906 NOPCB (GND)Bf(T_079BC88020180215122906 NOPCB (GND)BfPT_07C6D48020180215123058 NOPCB (GND)Bf0`T_0F05634020180215123248 NOPCB (GND)Bf0T_0F0580A020180215123328 NOPCB (GND)8? ]@P"MbP??ư>'dd?Y@[dddd@@?.AcA.AeAMbP?@@?Mb`?ư> $ 4@D@ =B?& .>??ư>ư>ư>ư>ư>ư>?I@?I@?I@& .>#i;@& .>-q=ư>MbP?-q=MbP?vIh%<=@@D@& .>?MbP?4@?{Gz?ꌠ9Y>)F@?+= _BKH9$@Y@& .>ư>?.AMbP??????I@Default analysis parameters. These parameters establish convergence and sufficient accuracy for most circuits. In case of convergence or accuracy problems click on the "hand " button to Open other parameter sets.?Xd I@nMbP?{Gz?{Gz?MbP????|=Hz>}Ô%ITNoname