1.1 Features

• 200-MHz C674x Fixed- and Floating-Point VLIW DSP
• C674x Instruction Set Features
  • Superset of the C67x+ and C64x+ ISAs
  • Up to 1600 MIPS and 1200 MFLOPS
  • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
  • 8-Bit Overflow Protection
  • Bit-Field Extract, Set, Clear
  • Normalization, Saturation, Bit-Counting
  • Compact 16-Bit Instructions
• C674x Two-Level Cache Memory Architecture
  • 32KB of L1P Program RAM/Cache
  • 32KB of L1D Data RAM/Cache
  • 64KB of L2 Unified Mapped RAM/Cache
  • Flexible RAM/Cache Partition (L1 and L2)
• Enhanced Direct Memory Access Controller 3 (EDMA3):
  • 2 Channel Controllers
  • 3 Transfer Controllers
  • 64 Independent DMA Channels
  • 16 Quick DMA Channels
  • Programmable Transfer Burst Size
• TMS320C674x Floating-Point VLIW DSP Core
  • Load-Store Architecture With Nonaligned Support
  • 64 General-Purpose Registers (32-Bit)
  • Six ALU (32- and 40-Bit) Functional Units
    • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
    • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
    • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
  • Two Multiply Functional Units:
    • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
      • 2 SP × SP → SP Per Clock
      • 2 SP × SP → DP Every Two Clocks
      • 2 SP × DP → DP Every Three Clocks
      • 2 DP × DP → DP Every Four Clocks
    • Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
  • Hardware Support for Modulo Loop Operation
  • Protected Mode Operation
  • Exceptions Support for Error Detection and Program Redirection
• Software Support
  • TI DSPBIOS™
  • Chip Support Library and DSP Library
• 1.8-V or 3.3-V LVCMOS I/Os (Except for DDR2 Interfaces)
• Two External Memory Interfaces:
  • EMIFA
    • NOR (8- or 16-Bit-Wide Data)
    • NAND (8- or 16-Bit-Wide Data)
    • 16-Bit SDRAM With 128-MB Address Space
  • DDR2/Mobile DDR Memory Controller With one of the Following:
    • 16-Bit DDR2 SDRAM With 256-MB Address Space
    • 16-Bit mDDR SDRAM With 256-MB Address Space
• One Configurable 16550-Type UART Module:
  • With Modem Control Signals
  • 16-Byte FIFO
  • 16x or 13x Oversampling Option
• One Serial Peripheral Interface (SPI) With Multiple Chip Selects
• Two Master and Slave Inter-Integrated Circuits
  (I²C Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth
• One Multichannel Audio Serial Port (McASP):
  • Two Clock Zones and 16 Serial Data Pins
  • Supports TDM, I2S, and Similar Formats
  • DIT-Capable
  • FIFO Buffers for Transmit and Receive
• One Multichannel Buffered Serial Port (McBSPs):
  • Supports TDM, I2S, and Similar Formats
  • AC97 Audio Codec Interface
  • Telecom Interfaces (ST-Bus, H100)
  • 128-Channel TDM
  • FIFO Buffers for Transmit and Receive
• Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
• One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
• Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
  • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
  • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
  • Dead-Band Generation
  • PWM Chopping by High-Frequency Carrier
  • Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules:
  • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
  • Single-Shot Capture of up to Four Event Timestamps
• Packages:
  • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
  • 361-Ball Pb-Free PBGA [ZWT Suffix],
    0.80-mm Ball Pitch
• Commercial or Extended Temperature

1.2 Applications

• Currency Inspection
• Biometric Identification
• Machine Vision (Low-End)

1.3 Description

The TMS320C6742 fixed- and floating-point DSP is a low-power applications processor based on a C674x DSP core. This DSP provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a
32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 64-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: one I²C Bus interface; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; one multichannel buffered serial port (McBSP) with FIFO buffers; one serial peripheral interface (SPI) with multiple chip selects; two 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; one UART interface (with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

1.4 Functional Block Diagram

Figure 1-1 Functional Block Diagram