SLVSAA6B April 2010 – November 2014 TPS54240
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation Output Current
- 7.3.3 Pulse Skip Eco-Mode
- 7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)
- 7.3.5 Error Amplifier
- 7.3.6 Voltage Reference
- 7.3.7 Adjusting The Output Voltage
- 7.3.8 Enable And Adjusting Undervoltage Lockout
- 7.3.9 Slow-Start / Tracking Pin (SS/TR)
- 7.3.10 Overload Recovery Circuit
- 7.3.11 Sequencing
- 7.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.13 Overcurrent Protection and Frequency Shift
- 7.3.14 Selecting the Switching Frequency
- 7.3.15 How to Interface to RT/CLK Pin
- 7.3.16 Powergood (PWRGD Pin)
- 7.3.17 Overvoltage Transient Protection
- 7.3.18 Thermal Shutdown
- 7.3.19 Small Signal Model for Loop Response
- 7.3.20 Simple Small Signal Model for Peak Current Mode Control
- 7.3.21 Small Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1
TPS54240 3.3-V Output Design
- 8.2.1.1 Design Requirements
- 8.2.1.2
Detailed Design Procedure
- 8.2.1.2.1 Selecting the Switching Frequency
- 8.2.1.2.2 Output Inductor Selection (LO)
- 8.2.1.2.3 Output Capacitor
- 8.2.1.2.4 Catch Diode
- 8.2.1.2.5 Input Capacitor
- 8.2.1.2.6 Slow-Start Capacitor
- 8.2.1.2.7 Bootstrap Capacitor Selection
- 8.2.1.2.8 Undervoltage Lock Out Set Point
- 8.2.1.2.9 Output Voltage And Feedback Resistors Selection
- 8.2.1.2.10 Compensation
- 8.2.1.2.11 Discontinuous Mode And Eco-Mode Boundary
- 8.2.1.2.12 Power Dissipation Estimate
- 8.2.1.3 Application Curves
- 8.2.2 TPS54240 Inverting Power Supply
- 8.2.3 TPS54240 Split Rail Power Supply
- 8.2.4 12-V To 3.8-V GSM Power Supply
- 8.2.5 24-V to 4.2-V GSM Power Supply
- 8.2.1
TPS54240 3.3-V Output Design
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
1 Features
- 3.5-V to 42-V Input Voltage Range
- 200-mΩ High-Side MOSFET
- High Efficiency at Light Loads With a Pulse Skipping Eco-Mode™
- 138-μA Operating Quiescent Current
- 1.3-μA Shutdown Current
- 100-kHz to 2.5-MHz Switching Frequency
- Synchronizes to External Clock
- Adjustable Slow Start and Sequencing
- UV and OV Power Good Output
- Adjustable UVLO Voltage and Hysteresis
- 0.8-V Internal Voltage Reference
- 10-Pin HVSSOP and 10-Pin 3-mm x 3-mm VSON Packages with PowerPAD™
- Supported by WEBENCH® Software Tool
2 Applications
- 12-V and 24-V Industrial and Commercial Low-Power Systems
- GSM, GPRS Modules in Fleet Management,
eMeters, and Security Systems
3 Description
The TPS54240 device is a 42-V, 2.5-A, step-down regulator with an integrated high-side MOSFET. Current mode control provides simple external compensation and flexible component selection. A low-ripple, pulse skip mode reduces the no load, regulated output supply current to 138 μA. Using the enable pin, shutdown supply current is reduced to 1.3 μA, when the enable pin is low.
Undervoltage lockout is internally set at 2.5 V, but it can be increased using the enable pin. The output voltage startup ramp is controlled by the slow-start pin that can also be configured for sequencing and tracking. An open-drain power good signal indicates the output is within 94% to 107% of its nominal voltage.
A wide switching frequency range allows efficiency and optimization of external component size. Frequency foldback and thermal shutdown protects the part during an overload condition.
The TPS54240 is available in 10-pin, thermally-enhanced HVSSOP and 10-pin 3-mm x 3-mm PowerPAD package.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPS54240 | HVSSOP (10) | 3.00 mm x 3.00 mm |
| VSON (10) |
- For all available packages, see the orderable addendum at the end of the datasheet.
Simplified Schematic
Efficiency vs Load Current
