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ZHCS779C March 2012 – July 2025 UCC28070 , UCC28070A

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DW|20
- MPDS173B
PW|20
- MPDS362A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

5.5 Electrical Characteristics

T_J = T_A = –40°C to 125°C, V_CC = 12V, GND = 0V, R_RT = 75k?, R_DMX = 68.1k?, R_RDM = R_SYN = 100k?, C_CDR = 2.2nF,
C_SS = C_VREF = 0.1μF, C_VCC = 1μF, I_VREF = 0mA (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
BIAS SUPPLY
V_CC(SHUNT)	V_CC shunt voltage⁽¹⁾		I_VCC = 10mA	23	25	27	V
I_VCC	Supply current	Disabled	V_VSENSE = 0V		7		mA
		Enabled	V_VSENSE = 3V (switching)		9	12	mA
		UVLO	V_CC = 7V			200	μA
		UVLO	V_CC = 9V		4	6	mA
V_UVLO	UVLO turnon threshold		Measured at VCC (rising)	9.8	10.2	10.6	V
V_UVLO	UVLO hysteresis		Measured at VCC (falling)		1		V
	VREF enable threshold		Measured at VCC (rising)	7.5	8	8.5	V
LINEAR REGULATOR
V_VREF	Reference voltage	No load	I_VREF = 0mA	5.82	6	6.18	V
		Load rejection	Measured as the change in V_VREF (I_VREF = 0mA and –2mA)	–12		12	mV
		Line rejection	Measured as the change in V_VREF (V_CC = 11V and 20V, I_VREF = 0μA)	–12		12	mV
PFC ENABLE
V_EN	Enable threshold		Measured at VSENSE (rising)	0.65	0.75	0.85	V
V_EN	Enable hysteresis				0.15		V
EXTERNAL PFC DISABLE
	Disable threshold		Measured at SS (falling)	0.5	0.6		V
	Hysteresis		V_VSENSE > 0.85V		0.15		V
OSCILLATOR
	Output phase shift		Measured between GDA and GDB	179	180	181	°
V_DMAX, V_RT, V_RDM	Timing regulation voltages		Measured at DMAX, RT, and RDM	2.91	3	3.09	V
f_PWM	PWM switching frequency, UCC28070A only		R_RT = 750k?, R_DMX = 681k?, V_RDM = 0V, V_CDR = 6V	9.75	10.25	10.75	kHz
	PWM switching frequency, UCC28070A and UCC28070		R_RT = 75k?, R_DMX = 68.1k?, V_RDM = 0V, V_CDR = 6V	95	100	105
	PWM switching frequency, UCC28070A and UCC28070		R_RT = 24.9k?, R_DMX = 22.6k?, V_RDM = 0V, V_CDR = 6V	270	290	330
D_MAX	Duty-cycle clamp		R_RT = 75k?, R_DMX = 68.1k?, V_RDM = 0V, V_CDR = 6V	92%	95%	98%
	Minimum programmable OFF-time		R_RT = 24.9k?, R_DMX = 22.6k?, V_RDM = 0V, V_CDR = 6V	50	150	250	ns
f_DM	Frequency dithering magnitude change in f_PWM		R_RDM = 316k?, R_RT = 75k?	2	3	4	kHz
f_DM	Frequency dithering magnitude change in f_PWM		R_RDM = 31.6k?, R_RT = 24.9k?	24	30	36	kHz
f_DR	Frequency dithering rate of change in f_PWM		R_RDM = 100k?, C_CDR = 2.2nF		3		kHz
f_DR	Frequency dithering rate of change in f_PWM		R_RDM = 100k?, C_CDR = 0.3nF		20		kHz
I_CDR	Dither rate current		Measured at CDR (sink and source)		±10		μA
	Dither disable threshold		Measured at CDR (rising)		5	5.25	V
CLOCK SYNCHRONIZATION
V_CDR	SYNC enable threshold		Measured at CDR (rising)		5	5.25	V
	SYNC propagation delay		V_CDR = 6V, measured from RDM (rising) to GDx (rising)		50	100	ns
	SYNC threshold (rising)		V_CDR = 6V, measured at RDM		1.2	1.5	V
	SYNC threshold (falling)		V_CDR = 6V, measured at RDM	0.4	0.7		V
t_SYNC	SYNC pulse width, minimum		Positive pulse	0.2			μs
	Maximum SYNC pulse duty cycle⁽²⁾				50%
VOLTAGE AMPLIFIER
	VSENSE voltage		In regulation, T_A = 25°C	2.97	3	3.03	V
	VSENSE voltage		In regulation	2.94	3	3.06	V
	VSENSE input bias current		In regulation		250	500	nA
	VAO high voltage		V_VSENSE = 2.9V	4.8	5	5.2	V
	VAO low voltage		V_VSENSE = 3.1V		0.05	0.5	V
g_MV	VAO transconductance		V_VSENSE = 2.8V to 3.2V, V_VAO = 3V		70		μS
	VAO sink current, overdriven limit		V_VSENSE = 3.5V, V_VAO = 3V		30		μA
	VAO source current, overdriven		V_VSENSE = 2.5V, V_VAO = 3V, SS = 3V		–30		μA
	VAO source current, overdriven limit + I_SRC		V_VSENSE = 2.5V, V_VAO = 3V		–130		μA
	Slew-rate correction threshold		Measured as V_VSENSE (falling) / V_VSENSE (regulation)	92%	93%	95%
	Slew-rate correction hysteresis		Measured at VSENSE (rising)		3	9	mV
I_SRC	Slew-rate correction current		Measured at VAO, in addition to VAO source current		–100		μA
	Slew-rate correction enable threshold		Measured at SS (rising)		4		V
	VAO discharge current		V_VSENSE = 0.5V, V_VAO = 1V		10		μA
SOFT START
I_SS	SS source current		V_VSENSE = 0.9V, V_SS = 1V		–10		μA
	Adaptive source current		V_VSENSE = 2V, V_SS = 1V		–1.5	–2.5	mA
	Adaptive SS disable		Measured as V_VSENSE – V_SS	–30	0	30	mV
	SS sink current		V_VSENSE = 0.5V, V_SS = 0.2V	0.5	0.9		mA
OVERVOLTAGE
V_OVP	OVP threshold		Measured as V_VSENSE (rising) / V_VSENSE (regulation)	104%	106%	108%
	OVP hysteresis		Measured at VSENSE (falling)		100		mV
	OVP propagation delay		Measured between VSENSE (rising) and GDx (falling)		0.2	0.3	μs
ZERO-POWER
V_ZPWR	Zero-power detect threshold		Measured at VAO (falling)	0.65	0.75		V
	Zero-power hysteresis				0.15		V
MULTIPLIER
k_MULT	Gain constant		V_VAO ≥ 1.5V, T_A = 25°C	16	17	18	μA
			V_VAO = 1.2V, T_A = 25°C	14.5	17	19.5
			V_VAO ≥ 1.5V	15	17	19
			V_VAO = 1.2V	13	17	21
I_IMO	Output current: zero		V_VINAC = 0.9V_PK, V_VAO = 0.8V	–0.2	0	0.2	μA
I_IMO	Output current: zero		V_VINAC = 0V, V_VAO = 5V	–0.2	0	0.2	μA
QUANTIZED VOLTAGE FEEDFORWARD
V_LVL1	Level 1 threshold⁽³⁾		Measured at VINAC (rising)	0.6	0.7	0.8	V
V_LVL2	Level 2 threshold		Measured at VINAC (rising)		1.0		V
V_LVL3	Level 3 threshold		Measured at VINAC (rising)		1.2		V
V_LVL4	Level 4 threshold		Measured at VINAC (rising)		1.4		V
V_LVL5	Level 5 threshold		Measured at VINAC (rising)		1.65		V
V_LVL6	Level 6 threshold		Measured at VINAC (rising)		1.95		V
V_LVL7	Level 7 threshold		Measured at VINAC (rising)		2.25		V
V_LVL8	Level 8 threshold		Measured at VINAC (rising)		2.6		V
CURRENT AMPLIFIERS
	CAOx high voltage			5.75	6		V
	CAOx low voltage					0.1	V
g_MC	CAOx transconductance				100		μS
	CAOx sink current, overdriven				50		μA
	CAOx source current, overdriven				–50		μA
	Input common mode range			0		3.6	V
	Input offset voltage		V_RSYNTH = 6V, T_A = 25°C	–4	–8	–13	mV
	Input offset voltage		V_RSYNTH = 6V	0	–8	–20	mV
	Input offset voltage			0	–8	–20	mV
	Phase mismatch		Measured as phase A input offset minus phase B input offset	–12	0	12	mV
	CAOx pulldown current		V_VSENSE = 0.5V, V_CAOx = 0.2V	0.5	0.9		mA
CURRENT SYNTHESIZER
V_RSYNTH	Regulation voltage		V_VSENSE = 3V, V_VINAC = 0V	2.91	3	3.09	V
V_RSYNTH	Regulation voltage		V_VSENSE = 3V, V_VINAC = 2.85V	0.1	0.15	0.2	V
	Synthesizer disable threshold		Measured at RSYNTH (rising)		5	5.25	V
	VINAC input bias current				0.25	0.5	μA
PEAK CURRENT LIMIT
	Peak current limit threshold		V_PKLMT = 3.3V, measured at CSx (rising)	3.27	3.3	3.33	V
	Peak current limit propagation delay		Measured between CSx (rising) and GDx (falling) edges		60	100	ns
PWM RAMP
V_RMP	PWM ramp amplitude			3.8	4	4.2	V
	PWM ramp offset voltage		T_A = 25°C, R_RT = 75k?	0.65	0.7		V
	PWM ramp offset temperature coefficient				–2		mV/°C
GATE DRIVE
	GDA, GDB output voltage, high, clamped		V_CC = 20V, C_LOAD = 1nF	11.5	13	15	V
	GDA, GDB output voltage, high		C_LOAD = 1nF	10	10.5		V
	GDA, GDB output voltage, low		C_LOAD = 1nF		0.2	0.3	V
	Rise time GDx		1V to 9V, C_LOAD = 1nF		18	30	ns
	Fall time GDx		9V to 1V, C_LOAD = 1nF		12	25	ns
	GDA, GDB output voltage, UVLO		V_CC = 0V, I_GDA, I_GDB = 2.5mA		0.7	2	V
THERMAL SHUTDOWN
	Thermal shutdown threshold				160		°C
	Thermal shutdown recovery				140		°C

(1) Excessive VCC input voltage or current damages the device. The VCC clamp does not protect the device from an unregulated bias supply. If an unregulated supply is used, TI recommends a series-connected fixed positive-voltage regulator such as a UA78L15A. See Section 5.1 for the limits on VCC voltage and current.

(2) Due to the influence of the synchronization pulse-width on the programmability of the maximum PWM switching duty-cycle (D_MAX), TI recommends to minimize the duty-cycle of the synchronization signal.

(3) The Level 1 threshold represents the zero-crossing detection threshold above which VINAC must rise to initiate a new input half-cycle, and below which VINAC must fall to terminate that half-cycle.