ZHCSLZ9C August 2020 – January 2024 UCC21732
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Power Ratings
- 5.6 Insulation Specifications
- 5.7 Safety-Related Certifications
- 5.8 Safety Limiting Values
- 5.9 Electrical Characteristics
- 5.10 Switching Characteristics
- 5.11 Insulation Characteristics Curves
- 5.12 Typical Characteristics
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Power Supply
- 7.3.2 Driver Stage
- 7.3.3 VCC and VDD Undervoltage Lockout (UVLO)
- 7.3.4 Active Pulldown
- 7.3.5 Short Circuit Clamping
- 7.3.6 External Active Miller Clamp
- 7.3.7 Overcurrent and Short Circuit Protection
- 7.3.8 2-Level Turn-Off
- 7.3.9 Fault ( FLT, Reset and Enable ( RST/EN)
- 7.3.10 Isolated Analog to PWM Signal Function
- 7.4 Device Functional Modes
-
8 Applications and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Input Filters for IN+, IN- and RST/EN
- 8.2.2.2 PWM Interlock of IN+ and IN-
- 8.2.2.3 FLT, RDY and RST/EN Pin Circuitry
- 8.2.2.4 RST/EN Pin Control
- 8.2.2.5 Turn-On and Turn-Off Gate Resistors
- 8.2.2.6 External Active Miller Clamp
- 8.2.2.7 Overcurrent and Short Circuit Protection
- 8.2.2.8 Isolated Analog Signal Sensing
- 8.2.2.9 Higher Output Current Using an External Current Buffer
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Revision History
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DW|16
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DW|16
訂購信息
4 Pin Configuration and Functions
Figure 4-1 UCC21732DW SOIC (16)Top
ViewTable 4-1 Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AIN | 1 | I | Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if unused. |
| OC | 2 | I | Over current detection pin, support lower threshold for SenseFET, DESAT, and Shunt resistor sensing. Tie to COM if unused. |
| COM | 3 | P | Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET |
| OUTH | 4 | O | Gate driver output pull up |
| VDD | 5 | P | Positive supply rail for gate drive voltage, Bypassing a >10-μF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin. |
| OUTL | 6 | O | Gate driver output pull down |
| CLMPE | 7 | O | External Active miller clamp, connecting this pin to the gate of the external miller clamp MOSFET. Leave floating if unused. |
| VEE | 8 | P | Negative supply rail for gate drive voltage. Bypassing a >10-μF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin. |
| GND | 9 | P | Input power supply and logic ground reference |
| IN+ | 10 | I | Non-inverting gate driver control input. Tie to VCC if unused. |
| IN– | 11 | I | Inverting gate driver control input. Tie to GND if unused. |
| RDY | 12 | O | Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other RDY signals |
| FLT | 13 | O | Active low fault alarm output upon overcurrent or short circuit. FLT is in open drain configuration and can be paralleled with other faults |
| RST/EN | 14 | I | The
RST/EN serves two purposes: 1) Enable / shutdown of the output side. The FET is turned off by a regular turn-off, if terminal EN is set to low; 2) Resets the OC condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000 ns. A reset of signal FLT is asserted at the rising edge of terminal RST/EN. For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The FET is turned off by a general turn-off, if terminal EN is set to low. |
| VCC | 15 | P | Input power supply from 3 V to 5.5 V, bypassing a >1-μF capacitor to GND. Place decoupling capacitor close to the pin. |
| APWM | 16 | O | Isolated Analog Sensing PWM output. Leave floating if unused. |
(1) P = Power, G = Ground, I = Input, O = Output