(凹凸)最新毛片婷婷99精品视频 ,国产精品无码一区二区久,无码日本大胆XXXX

SLUS352C January 1997 – December 2015 UC1846 , UC2846 , UC3846 , UC3847

PRODUCTION DATA.

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DW|16
N|16

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Supply Voltage (Pin 15)		40	V
Collector Supply Voltage (Pin 13)		40	V
Output Current, Source or Sink (Pins 11, 14)		500	mA
Analog Inputs (Pins 3, 4, 5, 6, 16)	–0.3	+V_IN	V
Reference Output Current (Pin 2)		–30	mA
Sync Output Current (Pin 10)		–5	mA
Error Amplifier Output Current (Pin 7)		–5	mA
Soft Start Sink Current (Pin 1)		50	mA
Oscillator Charging Current (Pin 9)		5	mA
Power Dissipation at T_A = 25°C		1000	mW
Power Dissipation at T_C = 25°C		2000	mW
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
	VREF terminal external capacitance	1		2.2	µF

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCx846/7		UNIT
		N or DW (PDIP or SOIC)	J or DW (CDIP or SOIC)
		16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	41.8	73.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	28.5	34.2	°C/W
R_θJB	Junction-to-board thermal resistance	21.8	38.0	°C/W
ψ_JT	Junction-to-top characterization parameter	13.0	7.7	°C/W
ψ_JB	Junction-to-board characterization parameter	21.7	37.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

T_A=–55°C to +125°C for UC1846/7; –40°C to +85°C for the UC2846/7; and 0°C to +70°C for the UC3846/7; V_IN=15 V, R_T=10k, C_T=4.7 nF, T_A=T_J (unless otherwise noted)

PARAMETER	TEST CONDITIONS	UC1846/7 UC2846/7			UC3846/7			UNIT
PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
REFERENCE
Output Voltage	T_J = 25°C, I_O = 1 mA	5.05	5.10	5.15	5.00	5.10	5.20	V
Line Regulation	V_IN = 8 V to 40 V		5	20		5	20	mV
Load Regulation	I_L = 1 mA to 10 mA		3	15		3	15	mV
Temperature Stability	Over Operating Range, ⁽¹⁾		0.4			0.4		mV/°C
Total Output Variation	Line, Load, and Temperature ⁽¹⁾	5.00		5.20	4.95		5.25	V
Output Noise Voltage	10 Hz ≤ f ≤10 kHz, T_J = 25°C⁽¹⁾		100			100		µV
Long Term Stability	T_J= 125°C, 1000 Hrs⁽¹⁾		5			5		mV
Short Circuit Output Current	V_REF = 0 V	–10	–45		–10	–45		mA
OSCILLATOR
Initial Accuracy	T_J = 25°C	39	43	47	39	43	47	kHz
Voltage Stability	V_IN =8 V to 40 V		–1%	2%		–1%	2%
Temperature Stability	Over Operating Range ⁽¹⁾		–1%			–1%
Sync Output High Level		3.9	4.35		3.9	4.35		V
Sync Output Low Level			2.3	2.5		2.3	2.5	V
Sync Input High Level	Pin 8 = 0 V	3.9			3.9			V
Sync Input Low Level	Pin 8 = 0 V			2.5			2.5	V
Sync Input Current	Sync Voltage = 3.9 V, Pin 8 = 0 V		1.3	1.5		1.3	1.5	mA
ERROR AMPLIFIER
Input Offset Voltage			0.5	5		0.5	10	mV
Input Bias Current			–0.6	–1		–0.6	–2	µA
Input Offset Current			40	250		40	250	nA
Common Mode Range	V_IN = 8 V to 40 V	0		V_IN - 2 V	0		V_IN - 2 V	V
Open Loop Voltage Gain	ΔV_O = 1.2 to 3 V, V_CM = 2 V	80	105		80	105		dB
Unity Gain Bandwidth	T_J = 25°C⁽¹⁾	0.7	1.0		0.7	1.0		MHz
CMRR	V_CM = 0 V to 38 V, V_IN = 40 V	75	100		75	100		dB
PSRR	V_IN = 8 V to 40 V	80	105		80	105		dB
Output Sink Current	V_ID = –15 mV to -5 V, V_PIN7 = 1.2 V	2	6		2	6		mA
Output Source Current	V_ID = 15 mV to -5 V, V_PIN7 = 2.5 V	–0.4	–0.5		–0.4	–0.5		mA
High Level Output Voltage	R_L = (Pin 7) 15 kΩ	4.3	4.6		4.3	4.6		V
Low Level Output Voltage	R_L = (Pin 7) 15 kΩ		0.7	1		0.7	1	V
CURRENT SENSE AMPLIFIER
Amplifier Gain	V_{PIN 3} = 0 V, Pin 1 Open⁽²⁾, ⁽³⁾	2.5	2.75	3.0	2.5	2.75	3.0	V
Maximum Differential Input Signal (V_{PIN 4}-V_{PIN 3})	Pin 1 Open ⁽²⁾; R_L (Pin 7) = 15 kW	1.1	1.2		1.1	1.2		V
Input Offset Voltage	V_{PIN 1} = 0.5 V, Pin 7 Open⁽²⁾		5	25		5	25	mV
CMRR	V_CM = 1 V to 12 V	60	83		60	83		dB
PSRR	V_IN = 8 V to 40 V	60	84		60	84		dB
Input Bias Current	V_{PIN 1} = 0.5 V, Pin 7 Open⁽²⁾		–2.5	–10		–2.5	–10	µA
Input Offset Current	V_{PIN 1} = 0.5 V, Pin 7 Open⁽²⁾		0.08	1		0.08	1	µA
Input Common Mode Range		0		V_IN-3	0		V_IN-3	V
Delay to Outputs	T_J = 25°C ⁽¹⁾		200	500		200	500	ns
CURRENT LIMIT ADJUST
Current Limit Offset	V_{PIN 3} = 0 V, V_{PIN 4} = 0 V, Pin 7 Open ⁽²⁾	0.45	0.5	0.55	0.45	0.5	0.55	V
Input Bias Current	V_{PIN 5} = V_REF, V_{PIN 6} = 0 V		–10	–30		–10	–30	µA
SHUTDOWN TERMINAL
Threshold Voltage		250	350	400	250	350	400	mV
Input Voltage Range		0		V_IN	0		V_IN	V
Minimum Latching Current (I_PIN1)	⁽⁵⁾	3.0	1.5		3.0	1.5		mA
Maximum Latching Current (I_PIN1)	⁽⁶⁾		1.5	0.8		1.5	0.8	mA
Delay to Outputs	T_J = 25°C ⁽¹⁾		300	600		300	600	ns
OUTPUT
Collector-Emitter Voltage		40			40			V
Collector Leakage Current	V_C = 40 V ⁽⁴⁾			200			200	µA
Output Low Level	I_SINK = 20 mA		0.1	0.4		0.1	0.4	V
Output Low Level	I_SINK = 100 mA		0.4	2.1		0.4	2.1	V
Output High Level	I_SOURCE = 20 mA	13	13.5		13	13.5		V
Output High Level	I_SOURCE = 100 mA	12	13.5		12	13.5		V
Rise Time	C_L = 1 nF, T_J = 25°C ⁽¹⁾		50	300		50	300	ns
Fall Time	C_L = 1 nF, T_J = 25°C ⁽¹⁾		50	300		50	300	ns
UNDERVOLTAGE LOCKOUT
Start-Up Threshold			7.7	8.0		7.7	8.0	V
Threshold Hysteresis			0.75			0.75		V
TOTAL STANDBY CURRENT
Supply Current			17	21		17	21	mA

(1) These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.

(2) Parameter measured at trip point of latch with VPIN 5 = VREF, VPIN 6 = 0 V.

(3) Amplifier gain defined as: G = ΔV_PIN7 / ΔV_PIN4; V_PIN4 = 0 to 1.0 V

(4) Applies to UC1846/UC2846/UC3846 only due to polarity of outputs.

(5) Current into Pin 1 ensured to latch circuit in shutdown state.

(6) Current into Pin 1 ensured not to latch circuit in shutdown state.

6.6 Typical Characteristics

UC1846 UC1847 UC2846 UC2847 UC3846 UC3847 slus352_typchar_1.gif

Figure 1. Error Amplifier Gain and Phase vs Frequency

UC1846 UC1847 UC2846 UC2847 UC3846 UC3847 slus352_typchar_2.gif

Figure 2. Error amplifier Open-Logic DC Gain vs Load Resistance