ZHCSCN9E June 2014 – June 2016 TUSB8041
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5
Register Maps
- 8.5.1 Configuration Registers
- 8.5.2 ROM Signature Register
- 8.5.3 Vendor ID LSB Register
- 8.5.4 Vendor ID MSB Register
- 8.5.5 Product ID LSB Register
- 8.5.6 Product ID MSB Register
- 8.5.7 Device Configuration Register
- 8.5.8 Battery Charging Support Register
- 8.5.9 Device Removable Configuration Register
- 8.5.10 Port Used Configuration Register
- 8.5.11 Device Configuration Register 2
- 8.5.12 USB 2.0 Port Polarity Control Register
- 8.5.13 UUID Registers
- 8.5.14 Language ID LSB Register
- 8.5.15 Language ID MSB Register
- 8.5.16 Serial Number String Length Register
- 8.5.17 Manufacturer String Length Register
- 8.5.18 Product String Length Register
- 8.5.19 Serial Number String Registers
- 8.5.20 Manufacturer String Registers
- 8.5.21 Product String Registers
- 8.5.22 Additional Feature Configuration Register
- 8.5.23 Device Status and Command Register
-
9 Applications and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
Discrete USB Hub Product
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Upstream Port Implementation
- 9.2.1.2.2 Downstream Port 1 Implementation
- 9.2.1.2.3 Downstream Port 2 Implementation
- 9.2.1.2.4 Downstream Port 3 Implementation
- 9.2.1.2.5 Downstream Port 4 Implementation
- 9.2.1.2.6 VBUS Power Switch Implementation
- 9.2.1.2.7 Clock, Reset, and Misc
- 9.2.1.2.8 TUSB8041 Power Implementation
- 9.2.1.3 Application Curves
- 9.2.1
Discrete USB Hub Product
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGC|64
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply Voltage Range | VDD Steady-state supply voltage | –0.3 | 1.4 | V |
| VDD33 Steady-state supply voltage | –0.3 | 3.8 | V | |
| Voltage Range | USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1] and USB_VBUS terminals | -0.3 | 1.4 | V |
| XI terminals | -0.3 | 2.45 | V | |
| All other terminals | -0.3 | 3.8 | V | |
| Storage temperature, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VDD(1) | 1.1V supply voltage | 0.99 | 1.1 | 1.26 | V | |
| VDD33 | 3.3V supply voltage | 3 | 3.3 | 3.6 | V | |
| USB_VBUS | Voltage at USB_VBUS PAD | 0 | 1.155 | V | ||
| TA | Operating free-air temperature | TUSB8041 | 0 | 70 | °C | |
| TUSB8041I | –40 | 85 | °C | |||
| TJ | Operating junction temperature | –40 | 105 | °C | ||
(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.
7.4 Thermal Information
| THERMAL METRIC(1) | TUSB8041 | UNIT | |
|---|---|---|---|
| RGC | |||
| 64 PINS | |||
| RθJA | Junction-to-ambient thermal resistance(2) | 26 | °C/W |
| RθJCtop | Junction-to-case (top) thermal resistance(3) | 11.5 | |
| RθJB | Junction-to-board thermal resistance(4) | 5.3 | |
| ψJT | Junction-to-top characterization parameter(5) | 0.2 | |
| ψJB | Junction-to-board characterization parameter(6) | 5.2 | |
| RθJCbot | Junction-to-case (bottom) thermal resistance(7) | 1.0 | |
(1) 有關(guān)傳統(tǒng)和新熱指標(biāo)的更多信息，請參見應(yīng)用報告《半導(dǎo)體和 IC 封裝熱指標(biāo)》（文獻(xiàn)編號：SPRA953）。
(2) 在 JESD51-2a 描述的環(huán)境中，按照 JESD51-7 的規(guī)定，在一個 JEDEC 標(biāo)準(zhǔn)高 K 電路板上進(jìn)行仿真，從而獲得自然對流條件下的結(jié)至環(huán)境熱阻抗。
(3) 通過在封裝頂部進(jìn)行冷板測試仿真來獲得結(jié)至外殼（頂部）熱阻。JEDEC 標(biāo)準(zhǔn)中沒有相關(guān)測試的描述，但 可在 ANSI SEMI 標(biāo)準(zhǔn) G30 - 88 中找到相應(yīng)的說明。
(4) 結(jié)至板熱阻，可按照 JESD51-8 中的說明在使用環(huán)形冷板夾具來控制 PCB 溫度的環(huán)境中進(jìn)行仿真來獲得。
(5) 結(jié)點(diǎn)至頂部特性參數(shù) ψJT 估算器件在實(shí)際系統(tǒng)中的結(jié)溫，可通過 JESD51-2a（第 6 節(jié)和第 7 節(jié)）介紹的步驟從獲得 RθJA 的仿真數(shù)據(jù)中獲取該溫度。
(6) 結(jié)點(diǎn)至電路板特性參數(shù) ψJB 估算器件在實(shí)際系統(tǒng)中的結(jié)溫，可通過 JESD51-2a（第 6 節(jié)和第 7 節(jié)）介紹的步驟從獲得 RθJA 的仿真數(shù)據(jù)中獲取該溫度。
(7) 通過在外露（電源）焊盤上進(jìn)行冷板測試仿真來獲得結(jié)至外殼（底部）熱阻。JEDEC 標(biāo)準(zhǔn)中沒有相關(guān)測試的描述，但 可在 ANSI SEMI 標(biāo)準(zhǔn) G30 - 88 中找到相應(yīng)的說明。
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7.5 Electrical Characteristics, 3.3-V I/O
over operating free-air temperature range (unless otherwise noted)| PARAMETER | OPERATION | TEST CONDITIONS | MIN | MAX | UNIT | |
| VIH | High-level input voltage(1) | VDD33 | 2 | VDD33 | V | |
| VIL | Low-level input voltage(1) | VDD33 | 0 | 0.8 | V | |
| JTAG pins only | 0 | 0.55 | ||||
| VI | Input voltage | 0 | VDD33 | V | ||
| VO | Output voltage(2) | 0 | VDD33 | V | ||
| tt | Input transition time (trise and tfall) | 0 | 25 | ns | ||
| Vhys | Input hysteresis(3) | 0.13 x VDD33 | V | |||
| VOH | High-level output voltage | VDD33 | IOH = -4 mA | 2.4 | V | |
| VOL | Low-level output voltage | VDD33 | IOL = 4 mA | 0.4 | V | |
| IOZ | High-impedance, output current(2) | VDD33 | VI = 0 to VDD33 | ±20 | µA | |
| IOZP | High-impedance, output current with internal pullup or pulldown resistor(4) | VDD33 | VI = 0 to VDD33 | ±250 | µA | |
| II | Input current(5) | VDD33 | VI = 0 to VDD33 | ±15 | µA | |
(1) Applies to external inputs and bidirectional buffers.
(2) Applies to external outputs and bidirectional buffers.
(3) Applies to GRSTz.
(4) Applies to pins with internal pullups/pulldowns.
(5) Applies to external input buffers.
7.6 Timing Requirements, Power-Up
| PARAMETER | DESCRIPTION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| td1 | VDD33 stable before VDD stable(3) | See (2) | ms | ||
| td2 | VDD and VDD33 stable before de-assertion of GRSTz | 3 | ms | ||
| tsu_io | Setup for MISC inputs(1) sampled at the de-assertion of GRSTz | 0.1 | µs | ||
| thd_io | Hold for MISC inputs(1) sampled at the de-assertion of GRSTz | 0.1 | µs | ||
| tVDD33_RAMP | VDD33 supply ramp requirements | 0.2 | 100 | ms | |
| tVDD_RAMP | VDD supply ramp requirements | 0.2 | 100 | ms |
(1) MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.
(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33.
(3) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.
Figure 2. Power-Up Timing Requirements