久久一级免费全裸视频,2020精品极品国产成人

ZHCSCO0B July 2014 – January 2016 TUSB8041-Q1

PRODUCTION DATA.

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

PAP|64

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Supply Voltage Range	V_DD Steady-state supply voltage	–0.3	1.4	V
Supply Voltage Range	V_DD33 Steady-state supply voltage	–0.3	3.8	V
Voltage Range	USB_SSRXP_UP, USB_SSRXN_UP, USB_SSRXP_DN[4:1], USB_SSRXN_DP[4:1] and USB_VBUS terminals	-0.3	1.4	V
	XI terminals	-0.3	2.45	V
	All other terminals	-0.3	3.8	V
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002 Classification Level H2⁽¹⁾		±2000	V
		Charged device model (CDM), per AEC Q100-011 Classification Level C4B	Corner pins	±750
			Other pins	±500

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
VDD	1.V1 supply voltage	0.99	1.1	1.26	V
VDD33	3.3V supply voltage	3	3.3	3.6	V
USB_VBUS	Voltage at USB_VBUS PAD	0		1.155	V
T_A	Operating free-air temperature	–40		85	°C
T_J	Operating junction temperature	–40		105	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TUSB8041-Q1	UNIT
		PAP
		64 PINS
R_θ_JA	Junction-to-ambient thermal resistance⁽²⁾	26.2	°C/W
R_θ_JCtop	Junction-to-case (top) thermal resistance⁽³⁾	11.5
R_θ_JB	Junction-to-board thermal resistance⁽⁴⁾	10.4
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	0.2
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	10.3
R_θ_JCbot	Junction-to-case (bottom) thermal resistance⁽⁷⁾	0.6

(1) 有關傳統(tǒng)和新熱指標的更多信息，請參見應用報告《半導體和 IC 封裝熱指標》（文獻編號：SPRA953）。

(2) 在 JESD51-2a 描述的環(huán)境中，按照 JESD51-7 的規(guī)定，在一個 JEDEC 標準高 K 電路板上進行仿真，從而獲得自然對流條件下的結(jié)至環(huán)境熱阻抗。

(3) 通過在封裝頂部進行冷板測試仿真來獲得結(jié)至外殼（頂部）熱阻。JEDEC 標準中沒有相關測試的描述，但可在 ANSI SEMI 標準 G30 - 88 中找到相應的說明。

(4) 結(jié)至板熱阻，可按照 JESD51-8 中的說明在使用環(huán)形冷板夾具來控制 PCB 溫度的環(huán)境中進行仿真來獲得。

(5) 結(jié)點至頂部特性參數(shù) ψ_JT 估算器件在實際系統(tǒng)中的結(jié)溫，可通過 JESD51-2a（第 6 節(jié)和第 7 節(jié)）介紹的步驟從獲得 R_θJA 的仿真數(shù)據(jù)中獲取該溫度。

(6) 結(jié)點至電路板特性參數(shù) ψ_JB 估算器件在實際系統(tǒng)中的結(jié)溫，可通過 JESD51-2a（第 6 節(jié)和第 7 節(jié)）介紹的步驟從獲得 R_θJA 的仿真數(shù)據(jù)中獲取該溫度。

(7) 通過在外露（電源）焊盤上進行冷板測試仿真來獲得結(jié)至外殼（底部）熱阻。JEDEC 標準中沒有相關測試的描述，但可在 ANSI SEMI 標準 G30 - 88 中找到相應的說明。

7.5 Electrical Characteristics, 3.3-V I/O

over operating free-air temperature range (unless otherwise noted)

PARAMETER		OPERATION	TEST CONDITIONS	MIN	MAX	UNIT
V_IH	High-level input voltage⁽¹⁾	VDD33		2	VDD33	V
V_IL	Low-level input voltage⁽¹⁾	VDD33		0	0.8	V
V_IL	Low-level input voltage⁽¹⁾	VDD33	JTAG pins only	0	0.55	V
V_I	Input voltage			0	VDD33	V
V_O	Output voltage⁽²⁾			0	VDD33	V
t_t	Input transition time (t_rise and t_fall)			0	25	ns
V_hys	Input hysteresis⁽³⁾				0.13 x VDD33	V
V_OH	High-level output voltage	VDD33	I_OH = -4 mA	2.4		V
V_OL	Low-level output voltage	VDD33	I_OL = 4 mA		0.4	V
I_OZ	High-impedance, output current⁽²⁾	VDD33	V_I = 0 to VDD33		±20	µA
I_OZP	High-impedance, output current with internal pullup or pulldown resistor⁽⁴⁾	VDD33	V_I = 0 to VDD33		±250	µA
I_I	Input current⁽⁵⁾	VDD33	V_I = 0 to VDD33		±15	µA

(1) Applies to external inputs and bidirectional buffers.

(2) Applies to external outputs and bidirectional buffers.

(3) Applies to GRSTz.

(4) Applies to pins with internal pullups/pulldowns.

(5) Applies to external input buffers.

7.6 Timing Requirements, Power-Up

PARAMETER	DESCRIPTION	MIN	MAX	UNIT
t_d1	VDD33 stable before VDD stable⁽³⁾	See ⁽²⁾		ms
t_d2	VDD and VDD33 stable before de-assertion of GRSTz	3		ms
t_{su_io}	Setup for MISC inputs⁽¹⁾ sampled at the de-assertion of GRSTz	0.1		µs
t_{hd_io}	Hold for MISC inputs⁽¹⁾ sampled at the de-assertion of GRSTz	0.1		µs
t_{VDD33_RAMP}	VDD33 supply ramp requirements	0.2	100	ms
t_{VDD_RAMP}	VDD supply ramp requirements	0.2	100	ms

(1) MISC pins sampled at de-assertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.

(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33.

(3) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.

Figure 2. Power-Up Timing Requirements

7.7 Hub Input Supply Current

Typical values measured at T_A = 25°C

PARAMETER	VDD33	VDD	UNIT
PARAMETER	3.3 V	1.1 V	UNIT
LOW POWER MODES
Power On (after Reset)	2.3	28	mA
Upstream Disconnect	2.3	28	mA
Suspend	2.5	33	mA
ACTIVE MODES (US state / DS State)
3.0 host / 1 SS Device and Hub in U1 / U2	49	225	mA
3.0 host / 1 SS Device and Hub in U0	49	366	mA
3.0 host / 2 SS Devices and Hub in U1 / U2	49	305	mA
3.0 host / 2 SS Devices and Hub in U0	49	508	mA
3.0 host / 3 SS Devices and Hub in U1 / U2	49	380	mA
3.0 host / 3 SS Devices and Hub in U0	49	661	mA
3.0 host / 4 SS Devices and Hub in U1 / U2	49	455	mA
3.0 host / 4 SS Devices and Hub in U0	49	778	mA
3.0 host / 1 SS Device in U0 and 1 HS Device	85	395	mA
3.0 host / 2 SS Devices in U0 and 2 HS Devices	99	554	mA
2.0 host / HS Device	45	63	mA
2.0 host / 4 HS Devices	76	86	mA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings(1)

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics, 3.3-V I/O

7.6 Timing Requirements, Power-Up

7.7 Hub Input Supply Current

7.1 Absolute Maximum Ratings⁽¹⁾