SLLSE32G November 2010 – November 2017 TUSB1310A
PRODUCTION DATA.
- 1Device Overview
- 2Revision History
- 3Pin Configuration and Functions
- 4Specifications
-
5Detailed Description
- 5.1 Overview
- 5.2 Functional Block Diagram
- 5.3 Feature Description
- 5.4 Device Functional Modes
- 5.5
Register Maps
- 5.5.1 Vendor ID and Product ID (00h-03h)
- 5.5.2 Function Control (04h-06h)
- 5.5.3 Interface Control (07h-09h)
- 5.5.4 OTG Control
- 5.5.5 USB Interrupt Enable Rising (0Dh-0Fh)
- 5.5.6 USB Interrupt Enable Falling (10h-12h)
- 5.5.7 USB Interrupt Status (13h)
- 5.5.8 USB Interrupt Latch (14h)
- 5.5.9 Debug (15h)
- 5.5.10 Scratch Register (16-18h)
- 6Application, Implementation, and Layout
- 7Device and Documentation Support
- 8Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- ZAY|175
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
5 Detailed Description
5.1 Overview
The USB physical layer handles the low-level USB protocol and signaling, which includes data serialization and deserialization, 8b/10b encoding, analog buffers, elastic buffers, and receiver detection. It shifts the clock domain of the data from the USB rate to one that is compatible with the link-layer controller.
The SuperSpeed USB contains SSTXP/SSTXN and SSRXP/SSRXN differential pairs and uses the PIPE to communicate with the link-layer controller. The Non-SuperSpeed USB has a DP/DM differential pair and communicates with the Link-Layer Controller through the ULPI. The reference clock of the TUSB1310A device is connected to an internal crystal oscillator, spread spectrum clock, and with a PLL, which provides clocks to all functional blocks and to the CLKOUT pin for the Link-Layer Controller.
A JTAG interface is used for IEEE1149.1 and IEEE1149.6 boundary scan.
5.2 Functional Block Diagram
5.3 Feature Description
5.3.1 Power On and Reset
The TUSB1310A device has two hardware reset pins, a chip reset RESETN and a logic reset PHY_RESETN. The RESETN is used only at Power On. The PHY_RESETN can be used as a functional reset. The ULPI register also has a software reset.
Until all power sources are supplied, the OUT_ENABLE pin can control the output driver enable. After all power sources are supplied, the chip reset RESETN and a ULPI soft reset is asserted by the Link Layer. The power-up sequence is described in Section 5.3.1.4.
5.3.1.1 RESETN and PHY_RESETN: Hardware Reset
The RESETN sets all internal states to initial values. The Link Layer must hold the PHY in reset through the RESETN until all power sources and the reference clock to the TUSB1310A device are stable. All pins used for strapping options must be set before RESETN deassertion as they are latched by reset deassertion. All strapping option pins have internal pullup or pulldown to set default values, but if any non-default values are desired, they need to be controlled externally by the Link-Layer Controller.
Table 5-1 Pin States in Chip Reset
| PIPE CONTROL PIN NAME | STATE | VALUE |
|---|---|---|
| TX_DETRX_LPBK | Inactive | 0 |
| TX_ELECIDLE | Active | 1 |
| TX_ONESZEROS | Inactive | 0 |
| RX_POLARITY | Inactive | 0 |
| POWER_DOWN | U2 | 10b |
| TX_MARGIN2-0 | Normal operating range | 000b |
| TX_DEEMP | –3.5 dB | 1 |
| RATE | 5.0 Gbps | 1 |
| TX_SWING | Full swing or half swing | 0 or 1 |
| RX_TERMINATION | Appropriate state | 0 or 1 |
5.3.1.2 ULPI Reset: Software Reset
After power-up, the Link-Layer Controller must set the reset bit in ULPI register. It resets the core but does not reset the ULPI interface or the ULPI registers.
During the ULPI reset, the ULPI_DIR is deasserted. After the reset, the ULPI_DIR is asserted again and the TUSB1310A device sends an RX CMD update to the Link Layer. During the reset, the link must ignore signals on the ULPI_DATA7-0 and must not access the TUSB1310A.
5.3.1.3 OUT_ENABLE: Output Enable
Digital IO buffers use two power supplies, core VDD1P1 and IO VDD1P8. During power up, OUT_ENABLE must be asserted low for proper operation.
5.3.1.4 Power-Up Sequence
Figure 5-1 shows the power-up sequence.
Figure 5-1 Power-Up Sequence
After proper power-supply sequencing, the reference clock on XI starts to operate. On the RESETN deassertion, REFCLKSEL1-0 is determined depending on the PHY_MODE pins, PLL is locked and the valid ULPI_CLK and the valid PCLK are driven.
After all stable clocks are provided, the TUSB1310A device allows the Link-Layer Controller to access by deasserting the ULPI_DIR. The Link-Layer Controller sets the Reset bit in the ULPI register. At the PIPE interface, the PHY_STATUS changes from high to low, which indicates that the TUSB1310A device is in the power state specified by the POWER_DOWN signal. After the PHY_STATUS change, the TUSB1310A device is ready for PIPE transactions.
5.3.2 Clocks
5.3.2.1 Clock Distribution
A source clock must be provided through XI or XO from an external crystal or from a square wave clock. The USB 3.0 PLL provides a clock to the PIPE that drives 250 MHz. The USB 2.0 PLL provides a 60-MHz clock to the ULPI.
5.3.2.2 Output Clock
The CLKOUT is used by the Link-Layer Controller or the MAC in low-power mode. A 120-MHz clock is available on the CLKOUT pin only in the USB U3 power state.
5.3.3 Power State Transition Time
The P1 to P0 transition time is the amount of time for the TUSB1310A device to return to P0 state, after having been in the P1 state. This time is measured from when the MAC sets the POWER_DOWN signals to P0 until the TUSB1310A device asserts PHY_STATUS. The TUSB1310A device asserts PHY_STATUS when it is ready to begin data transmission and reception.
The P2 to P0 transition time is the amount of time for the TUSB1310A device to return to the P0 state, after having been in the P2 state. This time is measured from when the MAC sets the POWER_DOWN signals to P0 until the TUSB1310A device asserts PHY_STATUS. The TUSB1310A device asserts PHY_STATUS when it is ready to begin data transmission and reception.
The P3 to P0 transition time is the amount of time for the TUSB1310A device to go to P0 state, after having been in the P3 state. Time is measured from when the MAC sets the POWER_DOWN signals to P0 until the TUSB1310A device deasserts PHY_STATUS. The TUSB1310A device asserts PHY_STATUS when it is ready to begin data transmission and reception.
5.3.4 Power Management
The SuperSpeed USB power state transition is controlled by the PIPE POWER_DOWN[1-0] and the Non-SuperSpeed USB power state is transitioned by setting suspendM bit in the ULPI Function control register through the ULPI or by asserting the ULPI_STP.
5.3.4.1 USB Power Management
The USB 3.0 specification improves power consumption by defining four power states, U0, U1, U2, and U3 while the PIPE specification defines P0, P1, P2 and P3. The POWER_DOWN pin states are mapped to LTSSM states as described in Table 5-2. For all power state transitions, the Link-Layer Controller must not begin any operational sequences or further power state transitions until the TUSB1310A device has indicated that the internal state transition is completed.
Table 5-2 Power States
| PIPE POWER STATE |
USB POWER STATE | PCLK | PLL | TRANSMITTING | RECEIVING | PHY_STATUS |
|---|---|---|---|---|---|---|
| P0 | U0, all other LTSSM states | On | On | Active or Idle or LFPS | Active or Idle | One cycle assertion |
| P1 | U1 | On | On | Idle or LFPS | Idle | One cycle assertion |
| P2 | U2, RxDetect, SS.Inactive | On | On | Idle or LFPS or RxDetect | Idle | One cycle assertion |
| P3 | U3, SS.disabled | Off. The PIPE is in an asynchronous mode. | Off | LFPS or RxDetect | Idle | PHY_STATUS is asserted before PCLK is turned off and deasserted when PCLK is fully off. |
When the Link-Layer Controller must transmit LFPS in P1, P2, or P3 state, it must deassert TX_ELECIDLE. The TUSB1310A device generates valid LFPS until the TX_ELECIDLE is asserted. The Link-Layer Controller must assert TX_ELECIDLE before transitioning to P0.
When RX_ELECIDLE is deasserted in P0, P1, P2, or P3, the TUSB1310A device receiver monitors for LFPS except during reset or when RX_TERMINATION is removed for electrical idle.
When the TUSB1310A device is in P0 and is actively transmitting; only RX_POLARITY can be asserted.
Table 5-3 PIPE Control Pin Matrix
| POWER STATE | TX_DETRX_LPBK | TX_ELECIDLE | DESCRIPTION |
|---|---|---|---|
| P0 | 0 | 0 | Transmitting data on TX_DATA |
| 0 | 1 | Not transmitting and is in electrical idle | |
| 1 | 0 | Goes into loopback mode | |
| 1 | 1 | Transmits LFPS signaling | |
| P1 | Don’t care | 0 | Transmits LFPS signaling |
| 1 | Not transmitting and is in electrical idle | ||
| P2 | Don’t care | 0 | Transmits LFPS signaling |
| 0 | 1 | Idle | |
| 1 | 1 | Does a receiver detection operation | |
| P3 | Don’t care | 0 | Transmits LFPS signaling |
| 1 | Does a receiver detection operation |
5.3.5 Receiver Status
The TUSB1310A device has an elastic buffer for clock tolerance compensation, the Link Partner detection, and some received data error detections. The receive data status from SSRXP/SSRXN differential pair presents on RX_STATUS2-0. If an error occurs during a SKP ordered-set (a set of symbols transmitted as a group), the error signaling has precedence. If more than one error occurs on a received byte, the errors have the following priority:
- 8B/10B decode error
- Elastic buffer overflow
- Elastic buffer underflow (cannot occur in nominal empty buffer model)
- Disparity error
5.3.5.1 Clock Tolerance Compensation
The receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a Link. The elastic buffer must be capable of holding enough symbols to handle worst case differences in frequency and worst case intervals between SKP ordered-sets. A SKP order-set is a set of symbols transmitted as a group. The SKP ordered-sets allows the receiver to adjust the data stream being received prevent the elastic buffer from either overflowing or under-flowing due to any clock tolerance differences.
The TUSB1310A device supports two models, nominal half-full buffer model and nominal empty-buffer mode. For the nominal half-full buffer model, the TUSB1310A device monitors the receive data stream. When a SKP ordered-set is received, the TUSB1310A device adds or removes one SKP order set from each SKP to manage its elastic buffer to keep the buffer as close to half full as possible. Only full SKP ordered sets are added or removed. When a SKP order set is added, the TUSB1310A device asserts an Add SKP code (001b) on the RX_STATUS for one clock cycle. When a SKP order set is removed, the RX_STATUS has a Remove SKP code (010b).
For the nominal empty-buffer model, the TUSB1310A device tries to keep the elasticity buffer as close to empty as possible. When no SKP ordered sets have been received, the TUSB1310A device is required to insert SKP ordered sets into the received data stream.
Table 5-4 RX_STATUS: SKP
| RX_STATUS2-0 | SKP ADDITION OR REMOVAL | LENGTH |
|---|---|---|
| 001b | 1 SKP Ordered Set added | One clock cycle |
| 010b | 1 SKP Ordered Set removed |
5.3.5.2 Receiver Detection
TX_DETRX_LPBK starts a receiver detection operation to determine if there is a receiver at the other end of the link. When the receiver detect sequence completes, the PHY_STATUS is asserted for one clock and drives the RX_STATUS signals to the appropriate code. When the TX_DETRX_LPBK signal is asserted, the Link-Layer Controller must leave the signal asserted until the PHY_STATUS pulse. When receiver detection is performed in P3, the PHY_STATUS shows the appropriate receiver detect value until the TX_DETRX_LPBK is deasserted.
Table 5-5 RX_STATUS: Receiver Detection
| RX_STATUS2-0 | DETECTED CONDITION | LENGTH |
|---|---|---|
| 000b | Receiver not present | One clock cycle |
| 011b | Receiver present |
5.3.5.3 8b/10b Decode Errors
When the TUSB1310A device detects an 8b/10b decode error, it asserts a SUB symbol in the data on the RX_DATA where the bad byte occurred. In the same clock cycle that the SUB symbol is asserted on the RX_DATA, the 8b/10b decode error code (100b) is asserted on the RX_STATUS. An 8b/10b decoding error has priority over all other receiver error codes and could mask out a disparity error occurring on the other byte of data being clocked onto the RX_DATA with the SUB symbol.
Table 5-6 8b/10b Decode Errors
| RX_STATUS2-0 | DETECTED ERROR | LENGTH |
|---|---|---|
| 100b | 8B/10B Decode Error | Clock cycles during the effected byte is transferred on RX_DATA15-0 |
5.3.5.4 Elastic Buffer Errors
When the elastic buffer overflows, data is lost during the reception of the data. The elastic buffer overflow error code (101b) is asserted on the RX_STATUS on the PCLK cycle the omitted data would have been asserted. The data asserted on the RX_DATA is still valid data, the elastic buffer overflow error code on the RX_STATUS just marks a discontinuity point in the data stream being received.
When the elastic buffer underflows, SUB symbols are inserted into the data stream on the RX_DATA to fill the holes created by the gaps between valid data. For every PCLK cycle a SUB symbol is asserted on the RX_DATA, an elastic buffer underflow error code (111b) is asserted on the RX_STATUS. In nominal empty-buffer mode, SKP ordered sets are transferred on RX_DATA and the underflow is not signaled.
Table 5-7 Elastic Buffer Errors
| RX_STATUS2-0 | DETECTED ERROR | LENGTH |
|---|---|---|
| 101b | Elastic Buffer overflow | Clock cycles the omitted data would have appeared |
| 110b | Elastic Buffer underflow | Clock cycles during the SUB symbol presence on RX_DATA15-0 |
5.3.5.5 Disparity Errors
When the TUSB1310A device detects a disparity error, it asserts a disparity error code (111b) on the RX_STATUS in the same PCLK cycle it asserts the erroneous data on the RX_DATA. The disparity code does not discern which byte on the RX_DATA is the erroneous data.
Table 5-8 Disparity Errors
| RX_STATUS2-0 | DETECTED ERROR | LENGTH |
|---|---|---|
| 111b | Disparity Error | Clock cycles during the effected byte is transferred on RX_DATA15-0 |
5.3.6 Loopback
The TUSB1310A device begins an internal-loopback operation from SSRXP/SSRXN differential pairs to SSTXP/SSTXN differential pairs when the TX_DETRX_LPBK is asserted while holding TX_ELECIDLE deasserted. The TUSB1310A device stops transmitting data to the SSTXP/SSTXN signaling pair from the TX_DATA and begins transmitting on the SSTXP/SSTXN signaling pair the data received at the SSRXP/SSRXN signaling pair. This data is not routed through the 8b/10b coding/encoding paths. While in the loopback operation, the received data is still sent to the RX_DATA. The data sent to the RX_DATA is routed through the 10b/8b decoder.
The TX_DETRX_LPBK deassertion terminates the loopback operation and returns to transmitting TX_DATA over the SSTXP/SSTXN signaling pair. The TUSB1310A device only transitions out of loopback on detection of LFPS signaling by transitioning to P2 state and starting the LFPS handshake.
5.3.7 Adaptive Equalizer
The adaptive equalizer dynamically adjusts the forward gain and peaking of the analog equalizer to minimize the jitter at the cross over point of the eye diagram, which allows for greater jitter tolerance in the RX.
5.4 Device Functional Modes
USB 3.0 is a physical SuperSpeed bus combined in parallel with a physical USB 2.0, according to the USB 3.0 Specification. Each PHY operates independently on a separate data bus. Following this specification, the USB architecture of the TUSB1310A device achieves different working modes. Simultaneous operation of USB 3.0 and USB 2.0 modes is not allowed for peripheral devices.
5.4.1 USB 3.0 Mode
At an electrical level, each SuperSpeed differential link is initialized by enabling its receiver termination. The transmitter is responsible for detecting the far end receiver termination as an indication of a bus connection and informing the link layer so the connect status can be factored into link operation and management. The SuperSpeed link is disabled, for example, when the low impedance receiver termination of a port is removed.
5.4.2 USB 2.0 Mode
When the TUSB1310A is connected to an electrical environment that only supports high-speed, full-speed, or low-speed connections, the SuperSpeed USB 3.0 connectivity is disabled. In this case, the USB 2.0 capabilities are compliant with the USB 2.0 specification.
5.4.3 ULPI Modes
The TUSB1310A device supports synchronous mode and low-power mode. The default mode is synchronous mode.
The synchronous mode is a normal operation mode. The ULPI_DATA are synchronous to ULPI_CLK. The low-power mode is used during power down and no ULPI_CLK. The TUSB1310A device sets ULPI_DIR to output and drives LineState signals and interrupts.
Table 5-9 ULPI Synchronous and Low-Power Mode Functions
| SYNCHRONOUS | LOW POWER |
|---|---|
| ULPI_CLK(OUT) | |
| ULPI_DATA7(I/O) | |
| ULPI_DATA6(I/O) | |
| ULPI_DATA5(I/O) | |
| ULPI_DATA4(I/O) | |
| ULPI_DATA3(I/O) | ULPI_INT (OUT) |
| ULPI_DATA2(I/O) | |
| ULPI_DATA1(I/O) | ULPI_LINESTATE1(OUT) |
| ULPI_DATA0(I/O) | ULPI_LINE_STATE0 (OUT) |
| ULPI_DIR(OUT) | |
| ULPI_STP(IN) | |
| ULPI_NXT(OUT) |
5.5 Register Maps
Table 5-10 Register Definitions
| ACCESS CODE | EXPANDED NAME | DESCRIPTION |
|---|---|---|
| Rd | Read | Register can be read. Read-only if this is the only mode given. |
| Wr | Write | Pattern on the data bus is written over all bits of the register. |
| S | Set | Pattern on the data bus is OR'd with and written into the register. |
| C | Clear | Pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit is set to zero (cleared). |
The TUSB1310A device contains the ULPI registers consisting of an immediate register set and an extended register set.
Table 5-11 Register Map
| REGISTER NAME | ADDRESS (6 BITS) | |||
|---|---|---|---|---|
| Rd | Wr | Set | Clr | |
| IMMEDIATE REGISTER SET | ||||
| Vendor ID Low | 00h | |||
| Vendor ID High | 01h | |||
| Product ID Low | 02h | |||
| Product ID High | 03h | |||
| Function Control | 04h–06h | 04h | 05h | 06h |
| Interface Control | 07h–09h | 07h | 08h | 09h |
| OTG Control | 0Ah–0Ch | 0Ah | 0Bh | 0Ch |
| USB Interrupt Enable Rising | 0Dh–0Fh | 0Dh | 0Eh | 0Fh |
| USB Interrupt Enable Falling | 10h–12h | 10h | 11h | 12h |
| USB Interrupt Status | 13h | 13h | ||
| USB Interrupt Latch | 14h | 14h | ||
| Debug | 15h | |||
| Scratch Register | 16h–18h | 16h | 17h | 18h |
| Reserved | 19h–2Eh | |||
5.5.1 Vendor ID and Product ID (00h-03h)
Table 5-12 Vendor ID and Product ID
| ADDRESS | BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|---|
| 00h | 7:00 | Vendor ID Low | Rd | 51h | Lower byte of vendor ID supplied by USB-IF |
| 01h | 7:00 | Vendor ID High | Rd | 04h | Upper byte of vendor ID supplied by USB-IF |
| 02h | 7:00 | Product ID Low | Rd | 10h | Lower byte of vendor ID supplied by vendor |
| 03h | 7:00 | Product ID High | Rd | 13h | Upper byte of vendor ID supplied by vendor |
5.5.2 Function Control (04h-06h)
Address: 04h-06h (Read), 04h (Write), 05h (Set), 06h (Clear)
Table 5-13 Function Control
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 1:0 | XcvrSelect | Rd, Wr, S, C | 1h | Selects the required transceiver speed 00b : Enable HS transceiver 01b: Enable FS transceiver 10b: Enable LS transceiver 11b: Enable FS transceiver for LS packets (FS preamble is automatically prepended) |
| 2 | TermSelect | Rd, Wr, S, C | 0 | Controls the internal 1.5-kΩ pullup resister and 45-Ω HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown. Because low speed peripherals never support full speed or hi-speed, providing the 1.5 kΩ on DM for low speed is optional. |
| 4:3 | OpMode | Rd, Wr, S, C | 00 | Selects the required bit encoding style during transmit 00 : Normal operation 01: Nondriving 10: Disable bit-stuff and NRZI encoding 11: Do not automatically add SYNC and EOP when transmitting. Must be used only for HS packets. |
| 5 | Reset | Rd, Wr, S, C | 0 | Active High transceiver reset. After the Link sets this bit, the TUSB1310A device must assert the ULPI_DIR and reset the ULPI. When the reset is completed, the PHY deasserts the ULPI_DIR and automatically clears this bit. After deasserting the ULPI_DIR, the PHY must re-assert the ULPI_DIR and send an RX CMD update on the Link-Layer Controller. The Link-Layer Controller must wait for the ULPI_DIR to deassert before using the ULPI bus. Does not reset the ULPI or ULPI register set. |
| 6 | SuspendM | Rd, Wr, S, C | 1h | Active low PHY suspend. Put the TUSB1310A device into low-power mode. The PHY can power down all blocks except the full speed receiver, OTG com-parators, and the ULPI pins. The PHY must automatically set this bit to 1 when low-power mode is exited. 0: Low-power mode 1: Powered |
| 7 | Reserved | Rd | 0 | Reserved |
5.5.3 Interface Control (07h-09h)
Address: 07-09h (Read), 07h (Write), 08h (Set), 09h (Clear)
Table 5-14 Interface Control
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 0 | Reserved | Rd | 0b | Reserved, only write a 0 to this bit |
| 1 | Reserved | Rd | 0b | Reserved, only write a 0 to this bit |
| 2 | Reserved | Rd | 0h | Reserved |
| 3 | ClockSuspendM | Rd, Wr, S, C | 0b | Active low clock suspend. Valid only in serial mode. Powers down the internal clock circuitry only. Valid only when SuspendM = 1. The TUSB1310A device must ignore ClockSuspend when SuspendM = 0. By default, the clock is not be powered in serial mode. 0 : Clock is not powered in serial mode 1 : Clock is powered in serial mode |
| 6:4 | Reserved | Rd | 0h | Reserved |
| 7 | Interface Protect Disable |
Rd, Wr, S, C | 0 | Controls internal pull-ups and pull-downs on both the ULPI_STP and the ULPI_DATA for protecting the ULPI when the Link-Layer Controller puts the signals to tri-state value. 0 Enables the pullup and pulldown 1 Disables the pullup and pulldown |
5.5.4 OTG Control
Address: 0Ah-0Ch (Read), 0Ah (Write), 0Bh (Set), 0Ch (Clear). Controls UTMI+ OTG functions of the PHY.
Table 5-15 OTG Control Register
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 0 | Reserved | Rd | 0b | This bit is not implemented and returns a 0b when read |
| 1 | DpPulldown | Rd, Wr, S, C | 1b | Enables the 15-kΩ pulldown resistor on D+ 0 Pulldown resistor not connected to D+ 1 Pulldown resistor connected to D+ |
| 2 | DmPulldown | Rd, Wr, S, C | 1h | Enables the 15-kΩ pulldown resistor on D– 0 Pulldown resistor not connected to D– 1 Pulldown resistor connected to D– |
| 7:3 | Reserved | Rd | 0h | These bits are not implemented and return zeros when read |
5.5.5 USB Interrupt Enable Rising (0Dh-0Fh)
Address: 0D-0Fh (Read), 0Dh (Write), 0Eh (Set), 0Fh (Clear)
Table 5-16 USB Interrupt Enable Rising
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 0 | Hostdisconnect Rise | Rd, Wr, S, C | 1b | Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). |
5.5.6 USB Interrupt Enable Falling (10h-12h)
Address: 10-12h (Read), 10h (Write), 11h (Set), 12h (Clear)
Table 5-17 USB Interrupt Enable Falling
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 0 | Hostdisconnect Fall | Rd, Wr, S, C | 1b | Generate an interrupt event notification when Host-disconnect changes from high to low. Applicable only in host. |
5.5.7 USB Interrupt Status (13h)
Address: 13h (Read-only)
Table 5-18 USB Interrupt Status
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 0 | Hostdisconnect Fall | Rd, Wr, S, C | 1b | Generate an interrupt event notification when Host-disconnect changes from high to low. Applicable only in host. |
5.5.8 USB Interrupt Latch (14h)
Address: 14h (Read-only with auto-clear)
Table 5-19 USB Interrupt Latch
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 0 | Hostdisconnect Fall | Rd, Wr, S, C | 1b | Set to 1b by the PHY when an unmasked event occurs on Host-disconnect. Cleared when this register is read. Applicable only in host mode. |
5.5.9 Debug (15h)
Address: 15h (Read-only)
Table 5-20 Debug
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 0 | LineState0 | Rd | 0 | Contains the current value of LineState0 |
| 1 | LineState1 | Rd | 0 | Contains the current value of LineState1 |
| 7:2 | Reserved | Rd | 0 | Reserved |
5.5.10 Scratch Register (16-18h)
Address: 16-18h (Read), 16h (Write), 17h (Set), 18h (Clear)
Table 5-21 Scratch Register
| BITS | NAME | ACCESS | RESET | DESCRIPTION |
|---|---|---|---|---|
| 7:0 | Scratch | Rd, Wr, S, C | 00 | Empty register byte for testing purposes. Software can read, write, set, and clear this register and the TUSB1310A device functionality is not be affected. |