| SUPPLY VOLTAGE (VIN) |
| VINUVLO |
VIN undervoltage lockout threshold |
No voltage hysteresis, rising and falling |
|
2.94 |
|
V |
| IVINSD |
Shutdown supply current |
VUVLO = 0 V, 4.5 V ≤ VVIN ≤ 42 V (60 V for HV) |
|
|
11.5 |
µA |
| IVIN |
Non-switching supply current |
VISENSE = 220 mV, 4.5V ≤ VVIN ≤ 42 V (60 V for HV) |
|
337 |
407 |
µA |
| UNDER VOLTAGE LOCKOUT (UVLO) |
| VUVLO |
UVLO threshold voltage |
Rising threshold |
1.12 |
1.22 |
1.30 |
V |
|
UVLO pin source current |
VUVLO = 1.5 V (device enabled) |
|
3.97 |
|
µA |
| VUVLO = 1 V (device disabled) |
|
1.05 |
|
| ANALOG CURRENT ADJUST (VIADJ, VISENSE) |
| VIADJ |
IADJ clamp voltage |
IIADJ = 1 µA |
|
1.8 |
|
V |
| IIADJ = 100 µA |
|
2.77 |
|
| VISENSE |
Current sense voltage |
VIADJ = 1.2 V, TJ = 25°C to 125°C |
191 |
200 |
210 |
mV |
| VIADJ = 0.18 V, TJ = 25°C to 125°C |
21.4 |
30.0 |
40.0 |
| IIADJ = 1 µA, TJ = 25°C to 125°C |
285 |
300 |
309 |
| IIADJ = 100 µA, TJ = 25°C to 125°C |
286 |
300 |
309 |
| Current sense voltage level |
180 mV ≤ VIADJ ≤ 1.8V |
|
VIADJ/6 |
|
| HIGH-SIDE MOSFET (BOOT, PH) |
| RDS(on) |
On-resistance |
VVIN = 4.5 V, (VBOOT – VPH) = 3.5 V |
|
255 |
|
mΩ |
| (VBOOT – VPH) = 6 V |
|
220 |
375 |
| VBOOT |
BOOT-PH voltage |
VPDIM = 3V |
|
6 |
|
V |
| IBOOT |
BOOT-PH current |
VPDIM = 0V, (VBOOT – VPH) = 5V |
|
93.9 |
|
µA |
| VBOOTUV |
BOOT-PH under voltage lockout |
Rising threshold |
|
2.25 |
2.81 |
V |
| Falling threshold |
1.42 |
1.99 |
|
| tON(min) |
Minimum on time |
VCOMP = 0 |
|
140 |
|
ns |
| ERROR AMPLIFIER (ISENSE, COMP) |
|
Input bias current |
VISENSE = 200 mV |
|
20 |
|
nA |
| gM(ea) |
Transconductance gain |
VIADJ = 1.2 V, 180 mV < VISENSE < 220 mV, VCOMP = 1 V |
|
331 |
|
µA/V |
|
DC gain |
VIADJ = 1.2 V , VISENSE = 0.2 V |
|
10 |
|
kV/V |
|
Bandwidth |
|
|
2.7 |
|
MHz |
|
Source/sink current |
VIADJ = 1.2 V , VCOMP = 1 V, VISENSE = 200 mV ± 100 mV |
|
±28 |
|
µA |
| CURRENT LIMIT |
|
Current limit threshold |
|
|
6 |
|
A |
| THERMAL SHUTDOWN |
| TSD |
Thermal shutdown |
|
|
165 |
|
°C |
|
Thermal shutdown hysteresis |
|
|
20 |
|
| TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK) |
| VRT |
RT/CLK regulated voltage |
RRT = 200 kΩ |
474 |
500 |
513 |
mV |
| fSW |
Switching frequency |
VVIN = 6 V, RRT = 200 kΩ |
447 |
557 |
648 |
kHz |
|
RT/CLK high threshold |
VVIN = 6 V |
|
1.49 |
1.81 |
V |
|
RT/CLK low threshold |
VVIN = 6 V |
0.63 |
1.02 |
|
V |
| PWM DIMMING (PDIM) |
| IPDIM |
PDIM source current |
VPDIM = 0 |
|
1.04 |
|
µA |
| VIH |
High-level input voltage |
|
|
1.34 |
1.45 |
V |
| VIL |
Low-level input voltage |
|
0.79 |
0.88 |
|