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ZHCSBU7B October 2013 – July 2015 TPS7B4250-Q1

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DBV|5
- MPDS018T

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Input voltage, unregulated input, V_IN⁽²⁾⁽³⁾	–20	45	V
Output voltage, regulated output, V_OUT	–1	22	V
Adjust input and enable input voltage, ADJ/EN⁽²⁾⁽³⁾	–0.3	22	V
ADJ Voltage minus input voltage (ADJ–V_IN), V_IN > 0 V		7	V
Operating junction temperature, T_J	–40	150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to ground, GND.

(3) Absolute maximum voltage.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽²⁾

		MIN	MAX	UNIT
V_IN	Unregulated input	4	40	V
V_OUT	regulated output	1.5	18	V
ADJ/EN	Adjust input and enable input voltage	1.5	18	V
ADJ–V_IN	ADJ voltage minus input voltage		5	V
C_OUT	Output capacitor requirements⁽¹⁾	1	50	µF
ESR_COUT	Output ESR requirements	0.001	20	Ω
T_J	Operating junction temperature	–40	150	°C

(1) The minimum output capacitance requirement is applicable for a worst-case capacitance tolerance of 30%.

(2) Within the functional range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.

6.4 Thermal Information

THERMAL METRIC⁽²⁾⁽¹⁾		TPS7B4250-Q1	UNIT
		DBV (SOT-23)
		5 PINS
R_θJA	Junction-to-ambient thermal resistance	171.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	81.1	°C/W
R_θJB	Junction-to-board thermal resistance	31.7	°C/W
ψ_JT	Junction-to-top characterization parameter	4.5	°C/W
ψ_JB	Junction-to-board characterization parameter	31.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) The thermal data is based on the JEDEC standard high K profile, JESD 51-7. Two-signal, two-plane, four-layer board with 2-oz. copper. The copper pad is soldered to the thermal land pattern. Also, correct attachment procedure must be incorporated.

(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

V_I = 13.5 V, 18 V ≥ V_ADJ/EN ≥ 1.5 V, T_J = –40ºC to 150ºC unless otherwise stated

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_UVLO	V_IN undervoltage detection	Ramp up V_I until the output turns on, V_ADJ = 1.5 V	3.65			V
V_UVLO	V_IN undervoltage detection	Ramp down V_I until the output turns off, V_ADJ = 1.5 V			3	V
ΔV_O	Output-voltage tracking accuracy	I_O = 100 µA to 1 mA, V_I = 4 V to 40 V, 1.5 V < V_ADJ < V_I – 0.3 V	–4		4	mV
ΔV_O	Output-voltage tracking accuracy	I_O = 1 mA to 50 mA, V_I = 4 V to 40 V, 1.5 V < V_ADJ < V_I – 1.5 V	–5		5	mV
ΔV_O(ΔIL)	Load regulation steady-state	I_O = 1 mA to 30 mA			4	mV
ΔV_O(ΔVI)	Line regulation steady-state	I_O = 10 mA, V_I= 6 V to 40 V			3	mV
PSRR	Power-supply ripple rejection	Frequency = 100 Hz, V_rip = 0.5 V_PP, I_O = 5 mA, C_O = 2.2 µF		60		dB
V_dropout	Dropout voltage, V_dropout = V_I – V_Q	I_O= 10 mA, V_I ≥ 4 V⁽¹⁾		150	265	mV
V_dropout	Dropout voltage, V_dropout = V_I – V_Q	I_O= 50 mA, V_I ≥ 4 V⁽¹⁾		550	1000	mV
I_L	Output-current limitation	V_Oshort to GND	100		500	mA
I_R	Reverse current at V_IN	V_I = 0 V, V_O = 20 V, V_ADJ = 5 V	–5		0	µA
I_RN1	Reverse current at negative input voltage	V_I = –20 V, V_O = 0 V, V_ADJ = 5 V	–5		0	µA
I_RN2	Reverse current at negative input voltage	V_I = –20 V, V_O = 20 V, V_ADJ = 5 V	–5		0	µA
T_SD	Thermal shutdown temperature	T_J increasing because of power dissipation generated by the IC		175		°C
I_Q	Current consumption	V_ADJ < 0.8 V, T_A ≤ 85°C⁽²⁾		7.5	15	µA
		V_ADJ < 0.8 V, T_A ≤ 125°C			20
		I_O = 0.5 mA, V_ADJ= 5 V		40	90
		I_O = 30 mA, V_ADJ= 5 V		150	350
I_ADJ	Adjust-input and enable-input current	V_ADJ = 5 V			1	µA
V_ADJ,low	Adjust and enable low signal valid	V_O = 0 V			0.8	V
V_ADJ,high	Adjust and enable high signal valid	\|V_O – V_ADJ\| < 5 mV	1.5		18	V

(1) Measured when the output voltage V_Q has dropped 10 mV from the typical value.

(2) Ensured by design.

6.6 Typical Characteristics

V_I = V_ADJ = 4 V	I_O = 10 mA

Figure 1. Dropout Voltage vs Temperature

V_I = 13.5 V	V_ADJ = 5 V

Figure 3. Ground Current vs Output Current

V_I = 13.5 V	V_ADJ = 5 V

Figure 5. Current-limit vs Temperature

V_ADJ = 5 V

Figure 7. Input Voltage vs Output Voltage

V_I = 9 to 16 V	2.2-µF ceramic output capacitor

Figure 9. Line Transient

V_I = 13.5 V	C_O = 2.2 µF	I_LOAD = 25 mA
V_ADJ = 5 V

Figure 11. Power-Supply Rejection Ratio vs Frequency

V_I = V_ADJ = 4 V

Figure 2. Dropout Voltage vs Output Current

V_I = 13.5 V

Figure 4. Ground Current vs Temperature

V_I = 13.5 V	V_ADJ = 5 V	I_O = 1 mA, 50 mA

Figure 6. Tracking Error vs Temperature

V_I = 13.5 V

Figure 8. Reference Voltage vs Output Voltage

I_O = 5 to 30 mA	2.2-µF ceramic output capacitor

Figure 10. Load Transient

Figure 12. ESR Stability vs Load Capacitance