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ZHCS922C May 2012 – October 2015 TPS54140A

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DGQ|10
- MPDS043F
DRC|10
- MPDS117L

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

DGQ|10
- PPTD325B
DRC|10
- QFND013N

訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating temperature range (unless otherwise noted).

		MIN	MAX	UNIT
Input voltage	VIN	–0.3	47	V
	EN⁽²⁾	–0.3	5
	BOOT		55
	VSENSE	–0.3	3
	COMP	–0.3	3
	PWRGD	–0.3	6
	SS/TR	–0.3	3
	RT/CLK	–0.3	3.6
Output voltage	PH–BOOT		8	V
	PH	–0.6	47
	PH, 10-ns Transient	–2	47
Voltage Difference	PAD to GND		±200	mV
Source current	EN		100	μA
	BOOT		100	mA
	VSENSE		10	μA
	PH	Current Limit		A
	RT/CLK		100	μA
Sink current	VIN	Current Limit		A
	COMP		100	μA
	PWRGD		10	mA
	SS/TR		200	μA
Operating junction temperature		–40	150	°C
Storage temperature		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) See the Enable and Adjusting Undervoltage Lockout section of this data sheet for details.

6.2 ESD Ratings

			VALUE	UNIT
DRC package (VSON)
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V
DGQ package (MSOP)
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible if necessary precautions are taken.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Supply input voltage range	3.5	42	V
V_O	Output voltage range	0.8	39	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS54140A		UNIT
		DGQ (MSOP)	DRC (VSON)
		10 PINS	10 PINS
R_θJA	Junction-to-ambient thermal resistance (standard board)	52.3	45.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	46.3	51.9	°C/W
R_θJB	Junction-to-board thermal resistance	33	20.5	°C/W
ψ_JT	Junction-to-top characterization parameter	1.6	0.8	°C/W
ψ_JB	Junction-to-board characterization parameter	32.7	20.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	5.9	5.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

T_J = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN PIN)
	Operating input voltage		3.5		42	V
	Internal undervoltage lockout threshold	No voltage hysteresis, rising and falling		2.5		V
	Shutdown supply current	EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V		1.3	4	μA
	Operating : nonswitching supply current	VSENSE = 0.83 V, VIN = 12 V, 25°C		116	136	μA
ENABLE AND UVLO (EN PIN)
	Enable threshold voltage	No voltage hysteresis, rising and falling	1.11	1.25	1.36	V
	Input current	Enable threshold +50 mV		–3.8		μA
	Input current	Enable threshold –50 mV		–0.9		μA
	Hysteresis current		1.91	2.95	3.99	μA
VOLTAGE REFERENCE
	Voltage reference	T_J = 25°C	0.792	0.8	0.808	V
	Voltage reference		0.784	0.8	0.816	V
HIGH-SIDE MOSFET
	On-resistance	VIN = 3.5 V, BOOT-PH = 3 V		300		mΩ
	On-resistance	VIN = 12 V, BOOT-PH = 6 V		200	410	mΩ
ERROR AMPLIFIER
	Input current			50		nA
	Error amplifier transconductance (g_M)	±2 μA < I_(COMP) < 2 μA, V_(COMP) = 1 V		97		μS
	Error amplifier transconductance (g_M) during slow start	±2 μA < I_(COMP) < 2 μA, V_(COMP) = 1 V, VSENSE = 0.4 V		26		μS
	Error amplifier dc gain	VSENSE = 0.8 V		10000		V/V
	Error amplifier bandwidth			2700		kHz
	Error amplifier source/sink	V_(COMP) = 1 V, 100 mV overdrive		±7		μA
	COMP to switch current transconductance			6		A/V
CURRENT LIMIT
	Current limit threshold	VIN = 12 V, T_J = 25°C	1.8	2.7		A
THERMAL SHUTDOWN
	Thermal shutdown			182		°C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
	Switching Frequency Range using RT mode		100		2500	kHz
f_SW	Switching frequency	R_T = 200 kΩ	450	581	720	kHz
	Switching Frequency Range using CLK mode		300		2200	kHz
	Minimum CLK pulse width			40		ns
	RT/CLK high threshold			1.9	2.2	V
	RT/CLK low threshold		0.5	0.7		V
	RT/CLK falling edge to PH rising edge delay	Measured at 500 kHz with RT resistor in series		60		ns
	PLL lock in time	Measured at 500 kHz		100		μs
SLOW START AND TRACKING (SS/TR)
	Charge current	V_SS/TR = 0.4 V		2		μA
	SS/TR-to-VSENSE matching	V_SS/TR = 0.4 V		45		mV
	SS/TR-to-reference crossover	98% nominal		1.0		V
	SS/TR discharge current (overload)	VSENSE = 0 V, V(SS/TR) = 0.4 V		112		μA
	SS/TR discharge voltage	VSENSE = 0 V		54		mV
POWER GOOD (PWRGD PIN)
V_VSENSE	VSENSE threshold	VSENSE falling		92%
		VSENSE rising		94%
		VSENSE rising		109%
		VSENSE falling		107%
	Hysteresis	VSENSE falling		2%
	Output high leakage	VSENSE = VREF, V_(PWRGD)= 5.5 V, 25°C		10		nA
	On resistance	I_(PWRGD) = 3 mA, VSENSE < 0.79 V		50		Ω
	Minimum VIN for defined output	V_(PWRGD)< 0.5 V, I_(PWRGD) = 100 μA		0.95	1.5	V