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SLUSCJ3A April 2016 – June 2016 TPS53632G

PRODUCTION DATA.

封裝選項

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input voltage	V5A	–0.3	6.0	V
	VBUS	–0.3	30.0
	VDD	–0.3	3.6
	COMP, CSP1, CSP2, CSN1, CSN2, DROOP, EN, FREQ-P, IMON, OCP-I, O-USR, RAMP, SCL, SDA, SLEWA, VFB, VINTF, VREF	–0.3	3.6
	GFB	–0.2	0.2
Output voltage	PGOOD	–0.3	3.6	V
Output voltage	PWM-LO, PWM-HI, SKIP	–0.3	6.0	V
Operating junction temperature, T_J		–40	150	°C
Storage temperature, T_stg			150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM) ESD stress voltage⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM) ESD stress voltage⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_I	Input voltage	V5A	4.5	5.5	V
		VBUS	–0.1	28
		VDD	3.1	3.5
		CSN1, CSN2, CSP1, CSP2, IMON, OCP-I, O-USR, RAMP, SCL, SDA, VFB, VINTF, VREF	–0.1	3.5
		COMP, DROOP, EN, FREQ-P, SLEWA	–0.1	5.5
		GFB	–0.1	0.1
V_O	Output voltage	PGOOD	–0.1	3.5	V
V_O	Output voltage	PWM-LO, PWM-HI, SKIP	–0.1	5.5	V
T_A	Operating ambient temperature		–10	105	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS53632G	UNITS
		RSM (VQFN)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	37.2	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	31.9	°C/W
R_θJB	Junction-to-board thermal resistance	8.1	°C/W
R_ψJT	Junction-to-top characterization parameter	0.4	°C/W
R_ψJB	Junction-to-board characterization parameter	7.9	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	2.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended free-air temperature range, V_V5A = 5.0 V, V_VDD = 3.3 V, V_GFB = GND, V_VFB = V_CORE (unless otherwise noted)

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY: CURRENTS, UVLO AND POWER-ON-RESET
I_V5-3P	V5A supply current	V_DAC < V_VFB < (V_DAC + 100 mV), EN = ‘HI’		3.6	6.0	mA
I_VDD-3P	VDD supply current	V_DAC < V_VFB < (V_DAC + 100 mV), EN = ‘HI’, digital buses idle		0.2	0.8	mA
I_V5STBY	V5A standby current	EN = ‘LO’		125	200	µA
I_VDDSTBY	VDD standby current	EN = ‘LO’		23	40
I_VDD-1P8	VINTF supply current	All conditions, digital buses idle		1.7	5.0
V_UVLOH	V5A UVLO ‘OK’ threshold	V_VFB < 200 mV, Ramp up, V_VDD > 3 V, EN = ’HI’, switching begins.	4.2	4.4	4.52	V
V_UVLOL	V5A UVLO fault threshold	Ramp down, EN = ’HI’, V_VDD > 3 V, V_VFB = 100 mV, restart if 5-V falls below V_POR then rises > V_UVLOH, or EN is toggled w/ V_V5A > V_UVLOH	4.00	4.2	4.35
V_POR	V5A fault latch reset threshold	Ramp down, EN = ‘HI’, V_VDD > 3 V. Can restart if 5-V rises to V_UVLOH and no other faults present.	1.2	1.9	2.5
V_3UVLOH	VDD UVLO ‘OK’ threshold	V_VFB < 200 mV. Ramp up, V_V5A > 4.5 V, EN = ’HI’, Switching begins.	2.5	2.8	3.0
V_3UVLOL	Fault threshold	Ramp down, EN = ’HI’, V5A > 4.5V, VFB = 100 mV, restart if 5-V dips below V_POR then rises > V_UVLOH or EN is toggled with 5 V > V_UVLOH	2.4	2.6	2.8
V_POR	VDD fault latch	Ramp down, EN = ‘HI’, V_V5A > 4.5 V, can restart if 5-V supply rises to V_UVLOH and no other faults present.	1.2	1.9	2.5
V_INTFUVLOH	VINTF UVLO OK	Ramp up, EN = ’HI’, V_V5A > 4.5 V, V_VFB = 100 mV	1.4	1.5	1.6
V_INTFUVLOL	VINTF UVLO falling	Ramp down, EN = ’HI’, V_V5A > 4.5 V, V_VFB = 100 mV	1.3	1.4	1.5
REFERENCES: DAC, VREF, VFB DISCHARGE
V_VIDSTP	VID step size	Change VID0 HI to LO to HI		10		mV
V_DAC1	VFB tolerance	No load active, 1.36 V ≤ V_VFB ≤ 1.52 V, I_OUT = 0 A	–9		9
V_DAC2	VFB tolerance	No load medium, 1.0 V ≤ V_VFB ≤ 1.35 V, I_OUT = 0 A	–8		8
V_DAC2	VFB tolerance	No load medium, 0.5 V ≤ V_VFB ≤ 0.99 V, I_OUT = 0 A	-7		7
V_VREF	VREF output	VREF output 4.5 V ≤ V_V5A ≤ 5.5 V, I_VREF = 0 A	1.66	1.700	1.74	V
V_VREFSRC	VREF output source	0 A ≤ I_REF ≤ 500 µA, HP-2	–4	-3		mV
V_VREFSNK	VREF output sink	–500 A ≤ I_REF ≤ 0 A, HP-2		3	4	mV
V_VBOOT	Internal VFB initial boot voltage	Initial DAC boot voltage	0.99	1.00	1.01	V
RAMP SETTINGS
V_RAMP	Compensation ramp	R_RAMP = 30 kΩ		60		mV
		R_RAMP = 56 kΩ		120
		R_RAMP = 100 kΩ		160
		R_RAMP ≥ 150 kΩ		40
VOLTAGE SENSE: VFB AND GFB
R_VFB	VFB/GFB Input resistance	Not in fault, disable or UVLO, V_VFB = V_DAC = 1.5 V, V_GFB = 0 V, measure from VFB to GFB	1			MΩ
V_DELGND	GFB Differential	GND to GFB		±100		mV
CURRENT MONITOR
VAL_ADC	IMON ADC output	∑?CS = 0 mV, A_IMON = 3.867		00h
		∑?CS = 1.5 mV, A_IMON = 3.867		19h
		∑?CS = 7.5 mV, A_IMON = 3.867		80h
		∑?CS = 15 mV, A_IMON = 3.867		FFh
LR_IMON	IMON linear range	Each phase, CSPx – CSNx	50			mV
CURRENT SENSE: OVER CURRENT PROTECTION, PHASE ADD AND DROP, AND PHASE BALANCE
V_OCPP	OCP voltage (valley current limit)	R_OCP-I = 20 kΩ	3.7	7.6	11.4	mV
		R_OCP-I = 24 kΩ	6.6	10.5	14.1
		R_OCP-I = 30 kΩ	10.6	14.5	18.0
		R_OCP-I = 39 kΩ	15.4	19.5	23.0
		R_OCP-I = 56 kΩ	21.3	25.4	29.0
		R_OCP-I = 75 kΩ	28.4	32.5	36.2
		R_OCP-I = 100 kΩ	36.3	40.5	44.0
		R_OCP-I = 150 kΩ	45.0	49.3	53.0
I_CS	CS pin input bias current	CSPx and CSNx	–500	0.2	500	nA
A_V-EA	Error amplifier total voltage gain⁽¹⁾	VFB to DROOP	80			dB
I_{EA_SR}	Error amplifier source current	I_DROOP, V_VFB = V_DAC + 50 mV, R_COMP = 1 kΩ		1		mA
I_{EA_SK}	Error amplifier sink current	I_DROOP, V_VFB = V_DAC – 50mV, R_COMP = 1 kΩ		–1		mA
A_CSINT	Internal current sense gain	Gain from CSPx – CSNx to PWM comparator, R_SKIP = Open	5.8	6.0	6.2	V/V
R_SFTSTP	Soft-stop transistor resistance	Connected to CSN1		100	200	Ω
R_VIN	VIN resistance	EN = HI		350	600	kΩ
R_VIN	VIN resistance	EN = LOW or STBY	10			MΩ
PROTECTION: OVP, UVP, PGOOD AND THERMAL SHUTDOWN
V_OVPH	Fixed OVP voltage	V_CSN1 > V_OVPH for 1 µs	1.60	1.70	1.80	V
V_PGDH	PGOOD high threshold	Measured at the VFB pin w/r/t VID code, device latches OFF	190		245	mV
V_PGDL	PGOOD low threshold	Measured at the VFB pin w/r/t VID code, device latches OFF	-348		-280	mV
PWM AND SKIP OUTPUTS: I/O VOLTAGE AND CURRENT
V_{P-S_L}	PWMx/SKIP - Low	PWM_ILOAD = ± 1 mA, SKIP_ILOAD= ± 100 µA		0.15	0.3	V
V_{P-S_H}	PWMx/SKIP - High	PWM_ILOAD = ± 1 mA, SKIP_ILOAD= ± 100 µA	4.2			V
LOGIC INTERFACE: VOLTAGE AND CURRENT
R_VRTTL	Pull-down resistance	V_SDA = 0.31	4		15	Ω
R_VRPG	Pull-down resistance	V_PGOOD= 0.31		36	50	Ω
I_VRTTLK	Logic leakage current	V_SCL= 1.8 V, V_SDA = 1.8 V, V_PGOOD = 3.3 V	-2	0.2	2	µA
V_IL	Low-level Input voltage	SCL, SDA; V_VINTF = 1.8 V			0.6	V
V_IH	High-level Input voltage	SCL, SDA; V_VINTF = 1.8 V	1.2			V
I_ENH	I/O leakage, EN	Leakage current , V_EN = 1.8 V		24	40	µA

(1) Specified by design. Not production tested.