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ZHCSGV1C June 2017 – March 2018 TPS25740B

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- MPQF124G

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- QFND136Y

訂購(gòu)信息

7.7 Switching Characteristics

Unless otherwise stated in a specific test condition the following conditions apply: –40°C ≤ T_J ≤ 125°C; 3 ≤ VDD ≤ 5.5 V, 4.65 V ≤ VPWR ≤ 25 V; HIPWR = GND, PSEL = GND, GD = VAUX, PCTRL = VAUX, AGND = GND; VAUX, VTX, bypassed with 0.1 µF, DVDD bypassed with 0.22 µF; all other pins open (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_VP	Delay from enabling external NFET until under-voltage and OCP protection are enabled	VBUS = GND		190		ms
t_STL	Source settling time, time from CTL1, CTL2, or CTL3 being changed until a PS_RDY USB PD message is transmitted to inform the sink is may draw full current. (refer to USB PD in 文檔支持)			260		ms
t_SR	Time that GDNG is disabled after a hard reset. This is t_SrcRecover. (refer to USB PD in 文檔支持)	T_J > T_J1		765		ms
t_HR	Time after hard reset is transmitted until GDNG is disabled. This is t_PSHardReset. (refer to USB PD in 文檔支持)			30		ms
t_CCDeb	Time until ENSRC is pulled low after sink attachment, this is the USB Type-C required debounce time for attachment detection called t_CCDebounce. (refer to USB Type-C in 文檔支持)			185		ms
t_ST	Delay after sink request is accepted until CTL1, CTL2, or CTL3 is changed. This is called t_{SnkTransition}. (refer to USB PD in 文檔支持)			30		ms
t_FLT	The time in between hard reset transmissions in the presence of a persistent supply fault.	GD = GND or VPWR = GND, sink attached		1395		ms
t_SH	The time in between retries (hard reset transmissions) in the presence of a persistent VBUS short.	VBUS = GND, sink attached		985		ms
t_ON	The time from ENSRC being pulled low until a hard reset is transmitted. Designed to be greater than t_SrcTurnOn. (refer to USB PD in 文檔支持)	GD = 0 V or VPWR = 0 V		600		ms
	Retry interval if USB PD sink stops communicating without being removed or if sink does not communicate after a fault condition. Time GDNG remains enabled before a hard reset is transmitted. This is the t_NoResponse time. (refer to USB PD in 文檔支持)	Sink attached		4.8		s
t_DVDD	Delay before DVDD is driven high	After sink attached			5	ms
t_GDoff	Turnoff delay, time until V_(GDNG) is below 10% of its initial value after the GD pin is low	V_GD: 5 V → 0 V in < 0.5 µs			5	µs
t_FOVP	Response time when VBUS exceeds the fast-OVP threshold	VBUS ↑ to GDNG OFF (V_(GDNG)below 10% its initial value)			30	µs
	OCP large signal response time	5 A enabled, V_(ISNS) -V_(VBUS): 0 V → 42 mV measured to GDNG transition start			30	µs
	Time until discharge is stopped after T_J1 is exceeded.	0 V ≤ V_(DSCG) ≤ 25 V			10	µs
	Digital output fall time	V_(PULLUP) = 1.8 V, C_L = 10 pF, R_(PULLUP) = 10 kΩ, V_(CTLx) or V_(ENSRC) : 70% V_PULLUP → 30% V_PULLUP	20		300	ps

Figure 1. Timing Illustration for t_VP, t_ST and t_STL, After Sink Attachment Negotiation to 12 V Then Back to 5 V. V_(SOVP) and V_(SUVP) are Disabled Around Voltage Transitions.

Figure 2. Timing Illustration for t_HR and t_SR, After Sink Attachment with Persistent T_J> T_J1

Figure 3. Timing Illustration for t_CcDeb and t_VP, Under Persistent Fault Condition

Figure 4. Timing Illustration for t_SH and t_VP, with VBUS Shorted to Ground

Figure 5. Timing Illustration for t_ON

Figure 6. Timing Illustration for t_ON

Figure 7. Timing Diagram for ENSRC and GDNG After Receiving a Hard Reset

Figure 8. Timing Diagram for ENSRC and GDNG After Transmitting a Hard Reset