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ZHCSA47E July 2012 – January 2018 TPS23751 , TPS23752

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PWP|20
- MHTS001H

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

PWP|20
- PPTD312C

訂購信息

6.6 Electric Characteristics - Controller Section

Unless otherwise noted, 40 V ≤ V_DD ≤ 57 V; V_CTL = V_MODE = V_SLPb = V_B; V_SRT = 0.5 V; V_APD = V_CS = V_ARTN = V_RTN; CLS, GATE, LED, SRD, T2P open; R_WAKE = 392 kΩ; R_DEN = 24.9 kΩ; R_T = 34 kΩ; C_VB = C_VC = 0.1 µF;
–40 ≤ T_J ≤ 125°C. Typical values are at 25°C. All voltages referred to V_SS.
V_C = 12 V, V_DEN = V_VSS, V_ARTN = V_RTN = V_SS

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_C (GATE DRIVE SUPPLY)
Output voltage; TPS23752 only		V_VDD = 48 V, Sleep mode		12	12.8	13.8	V
I_{VC_ST}	Startup source current	V_VDD = 48 V, V_C = 0 V		1.1	1.5	2.1	mA
I_{VC_ST}	Startup source current	V_VDD = 10.9 V, V_C = 8.6 V		0.9	1.3	1.8	mA
I_{VC_OP}	Operating current	V_VC = 12 V, V_CTL = V_B		0.9	1.8	3.0	mA
t_ST	Bootstrap start up time, C_VC = 22 µF	V_VDD = 48 V, measure time from V_VC (0) → V_CUV		103	155	203	ms
V_CUV	UVLO threshold	V_VC rising until V_SRD ↓		8.6	8.9	9.2	V
V_CUVH	UVLO threshold	Hysteresis		3	3.2	3.4	V
V_B (BIAS SUPPLY)
	Output voltage	7.5 V ≤ V_VC ≤ 18 V, 0 ≤ I_VB ≤ 5 mA		4.75	5.00	5.25	V
APD (AUXILIARY POWER DETECT)
V_APDEN	APD threshold voltage	V_APD ↑, measure with respect to ARTN		1.43	1.50	1.57	V
V_APDH	APD threshold voltage	Hysteresis		0.28	0.30	0.32	V
	Leakage current	V_APD = 18 V				10	µA
RT (OSCILLATOR)
F_SW	Switching frequency in PWM mode	R_T = 34.0 kΩ. Measure at GATE		226	251	276	kHz
F_VFO	Switching frequency in VFO mode	V_CTL = 1.75 V, R_T = 34.0 kΩ. Measure at GATE		105	135	165	kHz
D_MAX	Maximum duty cycle	V_CTL = V_B, Measure at GATE		75%	80%	85%
CTL (CONTROL – PWM INPUT)
V_{CTL_VFO}	V_CTL at PWM/VFO transition point	V_SRT = 0.5 V	V_CTL ↓ until V_SRD↑	1.90	2.00	2.10	V
		V_SRT = 0.5 V	Hysteresis ⁽¹⁾		35		mV
		V_SRT = 1.0 V	V_CTL ↓ until V_SRD↑	2.15	2.25	2.35	V
		V_SRT = 1.0 V	Hysteresis ⁽¹⁾		40.50		mV
T_SSD	Internal soft start delay time	V_CTL = 3.5 V, measure from switching start to V_CSMAX		1.87	3.01	5.09	ms
	Input resistance			70	105	145	kΩ
V_ZF	Zero frequency threshold (ZF)	V_CTL ↓ until GATE stops switching		1.40	1.50	1.60	V
V_ZDC	Zero duty cycle (ZDC) threshold (VFO disabled)	V_SRT = V_ARTN, V_CTL ↓ until GATE stops switching		1.55	1.75	1.95	V
	Gain, V_CS to V_CTL⁽¹⁾				5.0		V/V
CS (CURRENT SENSE)
V_CSMAX	Maximum threshold voltage	V_CS↑ until V_GATE ↓		0.22	0.25	0.28	V
V_{CS_VFO}	Peak V_CS in VFO mode	1.60 V ≤ V_CTL ≤ 1.90 V, V_SRT = 0.5 V, V_CS ↑ until V_GATE↓		40	50	60	mV
V_{CS_VFO}	Peak V_CS in VFO mode	1.85 V ≤ V_CTL ≤ 2.15 V, V_SRT= 1.0 V, V_CS↑ until V_GATE ↓		85	100	115	mV
V_PK	Internal slope compensation voltage, see Figure 1	D = D_MAX		32	40	50	mV
I_{CS_RAMP}	Ramp component of I_CS	D = D_MAX		12	16	25	µA
I_CSDC	DC component of I_CS			1	2	3	µA
D_{SLOPE_ST}	Slope compensation ramp start relative to switching period. Refer to Figure 1			30%	34%	39%
t₁	Turn off delay	V_CS = 0.3 V, measure t_prf50–50, see Figure 2			50	90	ns
t_BLNK	Blanking period			100	150	200	ns
	Off state pulldown resistance				290	500	Ω
GATE (GATE DRIVER)
	Peak source current	GATE high, pulsed measurement		0.35	0.60	1.00	A
	Peak sink current	GATE low, pulsed measurement		0.70	1.00	1.40	A
	Rise time ⁽¹⁾	t_prr10–90, C_GATE = 1 nF; see Figure 3			40		ns
	Fall time ⁽¹⁾	t_pff90–10, C_GATE = 1 nF; see Figure 3			27		ns
	Pull-up resistance					20	Ω
	Pull-down resistance					10	Ω
SRD (SYNCHRONOUS RECTIFIER DISABLE)
	Output low voltage	I_SRD = 2 mA sinking			0.25	0.45	V
	Leakage current	V_CTL = 1.75 V, V_SRD = 18 V				10	µA
SRT (SYNCHRONOUS RECTIFIER THRESHOLD)
	Leakage current	0 V ≤ V_SRT ≤ 5 V				1	µA
THERMAL SHUTDOWN
	Shutdown	T_Jrising		135	145	155	°C
	Hysteresis⁽¹⁾				20		°C

(1) Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty.