ZHCS851A March 2012 – September 2015 TLV320AIC3212
PRODUCTION DATA.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| AVDD1_18, AVDD2_18, AVDD4_18, AVDD_18 to AVSS1, AVSS2, AVSS4, AVSS respectively(2) | –0.3 | 2.2 | V | |
| AVDD3_33 to AVSS3 and RECVDD_33 to RECVSS | –0.3 | 3.9 | V | |
| DVDD to DVSS | –0.3 | 2.2 | V | |
| IOVDD to IOVSS | –0.3 | 3.9 | V | |
| HVDD_18 to AVSS | –0.3 | 2.2 | V | |
| CPVDD_18 to CPVSS | –0.3 | 2.2 | V | |
| SLVDD to SLVSS, SRVDD to SRVSS, SPK_V to SRVSS(3) | –0.3 | 6 | V | |
| Digital input voltage to ground | IOVSS – 0.3 | IOVDD + 0.3 | V | |
| Analog input voltage to ground | AVSS – 0.3 | AVDDx_18 + 0.3 | V | |
| VBAT | –0.3 | 6 | V | |
| Operating temperature | –40 | 85 | °C | |
| Junction temperature (TJ Max) | 105 | °C | ||
| Storage temperature | –55 | 125 | °C | |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2400 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
| MIN | NOM | MAX | UNIT | ||||
|---|---|---|---|---|---|---|---|
| AVDD1_18, AVDD2_18, AVDD4_18, AVDD_18 | Power supply voltage range | Referenced to AVSS1, AVSS2, AVSS4, AVSS respectively(1) TI recommends connecting each of these supplies to a single supply rail. | 1.5 | 1.8 | 1.95 | V | |
| AVDD3_33 , RECVDD_33 | Referenced to AVSS3 and RECVSS respectively | 1.65(3) | 3.3 | 3.6 | |||
| IOVDD | Referenced to IOVSS(1) | 1.1 | 3.6 | ||||
| DVDD(2) | Referenced to DVSS(1) | 1.8 | 1.95 | ||||
| CPVDD_18 | Power supply voltage range | Referenced to CPVSS (1) | 1.26 | 1.8 | 1.95 | V | |
| HVDD_18 | Referenced to AVSS(1) | Ground-centered configuration | 1.5(3) | 1.8 | 1.95 | ||
| Unipolar configuration | 1.65(3) | 3.6 | |||||
| SLVDD(1) | Power supply voltage range | Referenced to SLVSS(1) | 2.7 | 5.5 | V | ||
| SRVDD(1) | Power supply voltage range | Referenced to SRVSS(1) | 2.7 | 5.5 | V | ||
| SPK_V(1) | Power supply voltage range | Referenced to SRVSS(1) | 2.7 | 5.5 | V | ||
| VREF_SAR | External voltage reference for SAR | Referenced to AVSS | 1.8 | AVDDx_18 | V | ||
| PLL input frequency(4) | Clock divider uses fractional divide (D > 0), P=1, PLL_CLKIN_DIV=1, DVDD ≥ 1.65V (Refer to table in SLAU360, Maximum TLV320AIC3212 Clock Frequencies) |
10 | 20 | MHz | |||
| Clock divider uses integer divide (D = 0), P=1, PLL_CLKIN_DIV=1, DVDD ≥ 1.65V (Refer to table in SLAU360, Maximum TLV320AIC3212 Clock Frequencies) |
0.512 | 20 | MHz | ||||
| MCLK | Master clock frequency | MCLK; Master Clock Frequency; IOVDD ≥ 1.65V | 50 | MHz | |||
| MCLK; Master Clock Frequency; IOVDD ≥ 1.1V | 33 | ||||||
| SCL | SCL clock frequency | 400 | kHz | ||||
| HPL, HPR | Stereo headphone output load resistance | Single-ended configuration | 14.4 | 16 | Ω | ||
| SPKLP-SPKLM, SPKRP-SPKRM | Speaker output load resistance | Differential | 7.2 | 8 | Ω | ||
| RECP-RECM | Receiver output resistance | Differential | 24.4 | 32 | Ω | ||
| CIN | Charge pump input capacitor (CPVDD to CPVSS terminals) | 10 | µF | ||||
| CO | Charge pump output capacitor (VNEG terminal) | Type X7R | 2.2 | µF | |||
| CF | Charge pump flying capacitor (CPFCP to CPFCM terminals) | Type X7R | 2.2 | µF | |||
| TOPR | Operating temperature range | –40 | 85 | °C | |||
| THERMAL METRIC(1) | TLV320AIC3212 | UNIT | |
|---|---|---|---|
| YZF (DSBGA) | |||
| 81 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 39.1 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 0.1 | °C/W |
| RθJB | Junction-to-board thermal resistance | 12 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.7 | °C/W |
| ψJB | Junction-to-board characterization parameter | 11.5 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SAR ADC INPUTS | ||||||
| Analog Input | Input voltage range | IN1L/AUX1 or IN1R/AUX2 Selected | 0 | VREF_SAR | V | |
| Input impedance | 1 ÷ (f×CSAR_IN)(1) | kΩ | ||||
| Input capacitance, CSAR_IN | 25 | pF | ||||
| Input leakage current | 1 | µA | ||||
| Battery Input | VBAT Input voltage range | VBAT (Battery measurement) selected | 2.2 | 5.5 | V | |
| VBAT Input impedance | 5 | kΩ | ||||
| VBAT Input capacitance | 25 | pF | ||||
| VBAT Input leakage current | 1 | µA | ||||
| SAR ADC CONVERSION | ||||||
| Resolution | Programmable: 8-bit, 10-bit, 12-bit | 8 | 12 | Bits | ||
| No missing codes | 12-bit resolution | 11 | Bits | |||
| IN1L/ AUX1 |
Integral linearity | 12-bit resolution, SAR ADC clock = Internal Oscillator Clock, Conversion clock = Internal Oscillator / 4, External Reference = 1.8V(3) | ±1 | LSB | ||
| Offset error | ±1 | LSB | ||||
| Gain error | 0.07% | |||||
| Noise | DC voltage applied to IN1L/AUX1 = 1 V, SAR ADC clock = Internal Oscillator Clock, Conversion clock = Internal Oscillator / 4, External Reference = 1.8V(2)(3) | ±1 | LSB | |||
| VBAT | Accuracy | 12-bit resolution, SAR ADC clock = Internal Oscillator Clock, Conversion clock = Internal Oscillator / 4, Internal Reference = 1.25V | 2% | |||
| Offset error | ±2 | LSB | ||||
| Gain error | 1.5% | |||||
| Noise | DC voltage applied to VBAT = 3.6 V, 12-bit resolution, SAR ADC clock = Internal Oscillator Clock, Conversion clock = Internal Oscillator / 4, Internal Reference = 1.25V | ±0.5 | LSB | |||
| CONVERSION RATE | ||||||
| Normal conversion operation | 12-bit resolution, SAR ADC clock = 12 MHz External Clock, Conversion clock = External Clock / 4, External Reference = 1.8V(3). With Fast SPI reading of data. | 119 | kHz | |||
| High-speed conversion operation | 8-bit resolution,SAR ADC clock = 12 MHz External Clock, Internal Conversion clock = External Clock (Conversion accuracy is reduced.), External Reference = 1.8V(3). With Fast SPI reading of data. | 250 | kHz | |||
| VOLTAGE REFERENCE - VREF_SAR | ||||||
| Voltage range | Internal VREF_SAR | 1.25±0.05 | V | |||
| External VREF_SAR | 1.25 | AVDDx_18 | V | |||
| Reference Noise | CM=0.9V, Cref = 1μF | 32 | μVRMS | |||
| Decoupling Capacitor | 1 | μF | ||||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| AUDIO ADC (CM = 0.9 V) (1) (2) | ||||||
| Input signal level (0dB) | Single-ended, CM = 0.9 V | 0.5 | VRMS | |||
| Device Setup | 1-kHz sine wave input, Single-ended Configuration IN2R to Right ADC and IN2L to Left ADC, Rin = 20 kΩ, fs = 48 kHz, AOSR = 128, MCLK = 256*fs, PLL Disabled; AGC = OFF, Channel Gain = 0 dB, Processing Block = PRB_R1, Power Tune = PTM_R4 |
|||||
| SNR | Signal-to-noise ratio, A-weighted(1) (2) | Inputs AC-shorted to ground | 85 | 93 | dB | |
| IN1R, IN3R, IN4R each exclusively routed in separate tests to Right ADC and AC-shorted to ground IN1L, IN3L, IN4L each exclusively routed in separate tests to Left ADC and AC-shorted to ground |
93 | |||||
| DR | Dynamic range A-weighted(1) (2) | –60dB full-scale, 1-kHz input signal | 93 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3 dB full-scale, 1-kHz input signal | –87 | –70 | dB | |
| IN1R,IN3R, IN4R each exclusively routed in separate tests to Right ADC IN1L, IN3L, IN4L each exclusively routed in separate tests to Left ADC –3-dB full-scale, 1-kHz input signal |
–87 | |||||
| Gain Error | 1kHz sine wave input at -3dBFS, Single-ended configuration Rin = 20 K fs = 48 kHz, AOSR=128, MCLK = 256* fs, PLL Disabled AGC = OFF, Channel Gain=0 dB, Processing Block = PRB_R1, Power Tune = PTM_R4, CM=0.9 V |
0.1 | dB | |||
| Input Channel Separation | 1kHz sine wave input at –3 dBFS, Single-ended configuration IN1L routed to Left ADC, IN1R routed to Right ADC, Rin = 20 K AGC = OFF, AOSR = 128, Channel Gain=0 dB, CM=0.9 V |
110 | dB | |||
| Input Pin Crosstalk | 1-kHz sine wave input at –3 dBFS on IN2L, IN2L internally not routed. IN1L routed to Left ADC, AC-coupled to ground |
116 | dB | |||
| 1-kHz sine wave input at –3 dBFS on IN2R, IN2R internally not routed. IN1R routed to Right ADC, AC-coupled to ground |
||||||
| Single-ended configuration Rin = 20 kΩ, AOSR=128 Channel Gain=0 dB, CM=0.9 V | ||||||
| PSRR | 217Hz, 100mVpp signal on AVDD_18, AVDDx_18 Single-ended configuration, Rin=20 kΩ, Channel Gain=0 dB; CM=0.9 V |
59 | dB | |||
| AUDIO ADC (CM = 0.75 V) | ||||||
| Input signal level (0dB) | Single-ended, CM=0.75 V, AVDD_18, AVDDx_18 = 1.5 V | 0.375 | VRMS | |||
| Device Setup | 1-kHz sine wave input, Single-ended Configuration IN2R to Right ADC and IN2L to Left ADC, Rin = 20 K, fs = 48 kHz, AOSR = 128, MCLK = 256*fs, PLL Disabled; AGC = OFF, Channel Gain = 0 dB, Processing Block = PRB_R1, Power Tune = PTM_R4 |
|||||
| SNR | Signal-to-noise ratio, A-weighted (1) (2) | Inputs AC-shorted to ground | 91 | dB | ||
| IN1R, IN3R, IN4R each exclusively routed in separate tests to Right ADC and AC-shorted to ground IN1L, IN3L, IN4L each exclusively routed in separate tests to Left ADC and AC-shorted to ground |
91 | dB | ||||
| DR | Dynamic range A-weighted(1) (2) | –60-dB full-scale, 1-kHz input signal | 91 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3-dB full-scale, 1-kHz input signal | –85 | dB | ||
| AUDIO ADC (Differential Input, CM = 0.9 V) | ||||||
| Input signal level (0dB) | Differential, CM=0.9 V, AVDD_18, AVDDx_18 = 1.8 V | 1 | VRMS | |||
| Device Setup | 1-kHz sine wave input, Differential Configuration IN1L, IN1R Routed to Right ADC, IN2L, IN2R Routed to Left ADC Rin = 20 kΩ, fs = 48 kHz, AOSR=128, MCLK = 256* fs, PLL Disabled, AGC = OFF, Channel Gain = 0 dB, Processing Block = PRB_R1, Power Tune = PTM_R4 |
|||||
| SNR | Signal-to-noise ratio, A-weighted (1) (2) | Inputs AC-shorted to ground | 94 | dB | ||
| DR | Dynamic range A-weighted(1) (2) | –60-dB full-scale, 1-kHz input signal | 94 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3dB full-scale, 1-kHz input signal | –88 | dB | ||
| Gain Error | 1-kHz sine wave input at –3 dBFS, Differential configuration Rin = 20 kΩ, fs = 48 kHz, AOSR=128, MCLK = 256* fs, PLL Disabled AGC = OFF, Channel Gain=0 dB, Processing Block = PRB_R1, Power Tune = PTM_R4, CM=0.9 V |
0.1 | dB | |||
| Input Channel Separation | 1kHz sine wave input at –3 dBFS, Differential configuration IN1L/IN1R differential signal routed to Right ADC, IN2L/IN2R differential signal routed to Left ADC, Rin = 20 kΩ AGC = OFF, AOSR = 128, Channel Gain=0 dB, CM=0.9 V |
107 | dB | |||
| Input Pin Crosstalk | 1-kHz sine wave input at –3 dBFS on IN2L/IN2R, IN2L/IN2R internally not routed. IN1L/IN1R differentially routed to Right ADC, AC-coupled to ground |
109 | dB | |||
| 1-kHz sine wave input at –3 dBFS on IN2L/IN2R, IN2L/IN2R internally not routed. IN3L/IN3R differentially routed to Left ADC, AC-coupled to ground |
||||||
| Differential configuration Rin = 20 kΩ, AOSR=128 Channel Gain=0 dB, CM=0.9 V | ||||||
| PSRR | 217 Hz, 100 mVpp signal on AVDD_18, AVDDx_18 Differential configuration, Rin=20 K, Channel Gain=0 dB; CM=0.9 V |
59 | dB | |||
| AUDIO ADC | ||||||
| ADC programmable gain amplifier gain | IN1 - IN3, Single-Ended, Rin = 10 K, PGA gain set to 0 dB | 0 | dB | |||
| IN1 - IN3, Single-Ended, Rin = 10 K, PGA gain set to 47.5 dB | 47.5 | dB | ||||
| IN1 - IN3, Single-Ended, Rin = 20 K, PGA gain set to 0 dB | –6 | dB | ||||
| IN1 - IN3, Single-Ended, Rin = 20 K, PGA gain set to 47.5 dB | 41.5 | dB | ||||
| IN1 - IN3, Single-Ended, Rin = 40 K, PGA gain set to 0 dB | –12 | dB | ||||
| IN1 - IN3, Single-Ended, Rin = 40 K, PGA gain set to 47.5 dB | 35.5 | dB | ||||
| IN4, Single-Ended, Rin = 20 K, PGA gain set to 0 dB | –6 | dB | ||||
| IN4, Single-Ended, Rin = 20 K, PGA gain set to 47.5 dB | 41.5 | dB | ||||
| ADC programmable gain amplifier step size | 1-kHz tone | 0.5 | dB | |||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ANALOG BYPASS TO RECEIVER AMPLIFIER, DIRECT MODE | ||||||
| Device Setup | Load = 32Ω (differential), 56pF; Input CM=0.9V; Output CM=1.65V; IN1L routed to RECP and IN1R routed to RECM; Channel Gain=0dB |
|||||
| Full scale differential input voltage (0dB) | 1 | VRMS | ||||
| Gain Error | 707mVrms (-3dBFS), 1-kHz input signal | 0.5 | dB | |||
| Noise, A-weighted(1) | Idle Channel, IN1L and IN1R ac-shorted to ground | 13 | μVRMS | |||
| THD+N | Total Harmonic Distortion plus Noise | 707mVrms (-3dBFS), 1-kHz input signal | –88 | dB | ||
| ANALOG BYPASS TO HEADPHONE AMPLIFIER, PGA MODE | ||||||
| Device Setup | Load = 16 Ω (single-ended), 56 pF; HVDD_18 = 3.3 V Input CM=0.9 V; Output CM=1.65 V IN1L routed to ADCPGA_L, ADCPGA_L routed through MAL to HPL; and IN1R routed to ADCPGA_R, ADCPGA_R routed through MAR to HPR; Rin = 20 K; Channel Gain = 0 dB |
|||||
| Full scale input voltage (0 dB) | 0.5 | VRMS | ||||
| Gain Error | 446 mVrms (–1dBFS), 1-kHz input signal | –1.2 | dB | |||
| Noise, A-weighted(1) | Idle Channel, IN1L and IN1R AC-shorted to ground | 6 | μVRMS | |||
| THD+N | Total Harmonic Distortion plus Noise | 446 mVrms (–1dBFS), 1-kHz input signal | –81 | dB | ||
| ANALOG BYPASS TO HEADPHONE AMPLIFIER (GROUND-CENTERED CIRCUIT CONFIGURATION), PGA MODE | ||||||
| Device Setup | Load = 16 Ω (single-ended), 56 pF; Input CM=0.9 V; IN1L routed to ADCPGA_L, ADCPGA_L routed through MAL to HPL; and IN1R routed to ADCPGA_R, ADCPGA_R routed through MAR to HPR; Rin = 20 K; Channel Gain = 0 dB |
|||||
| Full scale input voltage (0dB) | 0.5 | VRMS | ||||
| Gain Error | 446 mVrms (-1dBFS), 1-kHz input signal | –1 | dB | |||
| Noise, A-weighted(1) | Idle Channel, IN1L and IN1R ac-shorted to ground | 11 | μVRMS | |||
| THD+N | Total Harmonic Distortion plus Noise | 446mVrms (-1dBFS), 1-kHz input signal | –67 | dB | ||
| ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE | ||||||
| Device Setup | Load = 10KOhm (single-ended), 56pF; Input and Output CM=0.9V; IN1L routed to ADCPGA_L and IN1R routed to ADCPGA_R; Rin = 20k ADCPGA_L routed through MAL to LOL and ADCPGA_R routed through MAR to LOR; Channel Gain = 0dB |
|||||
| Full scale input voltage (0dB) | 0.5 | VRMS | ||||
| Gain Error | 446mVrms (-1dBFS), 1-kHz input signal | –0.7 | dB | |||
| Noise, A-weighted(1) | Idle Channel, IN1L and IN1R ac-shorted to ground |
6 | μVRMS | |||
| Channel Gain=40dB, Inputs ac-shorted to ground, Input Referred |
3 | μVRMS | ||||
| ANALOG BYPASS TO LINE-OUT AMPLIFIER, DIRECT MODE | ||||||
| Device Setup | Load = 10 kΩ (single-ended), 56 pF; Input and Output CM=0.9 V; IN1L routed to LOL and IN1R routed to LOR; Channel Gain = 0 dB |
|||||
| Full scale input voltage (0dB) | 0.5 | VRMS | ||||
| Gain Error | 446mVrms (-1dBFS), 1-kHz input signal | –0.3 | dB | |||
| Noise, A-weighted(1) | Idle Channel, IN1L and IN1R AC-shorted to ground |
3 | μVRMS | |||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| MICROPHONE BIAS (MICBIAS or MICBIAS_EXT) | ||||||
| Bias voltage | CM=0.9V, AVDD3_33 = 1.8 V | |||||
| Micbias Mode 0 | 1.63 | V | ||||
| Micbias Mode 3 | AVDD3_33 | V | ||||
| CM=0.75V, AVDD3_33 = 1.8 V | ||||||
| Micbias Mode 0 | 1.36 | V | ||||
| Micbias Mode 3 | AVDD3_33 | V | ||||
| MICROPHONE BIAS (MICBIAS or MICBIAS_EXT) | ||||||
| Bias voltage | CM=0.9 V, AVDD3_33 = 3.3 V | |||||
| Micbias Mode 0 | 1.63 | V | ||||
| Micbias Mode 1 | 2.36 | V | ||||
| Micbias Mode 2 | 2.91 | V | ||||
| Micbias Mode 3 | AVDD3_33 | V | ||||
| CM=0.75 V, AVDD3_33 = 3.3 V | ||||||
| Micbias Mode 0 | 1.36 | V | ||||
| Micbias Mode 1 | 1.97 | V | ||||
| Micbias Mode 2 | 2.42 | V | ||||
| Micbias Mode 3 | AVDD3_33 | V | ||||
| Output Noise | CM=0.9V, Micbias Mode 2, A-weighted, 20-Hz to 20-kHz bandwidth, Current load = 0 mA. |
26 | μVRMS | |||
| 184 | nV/√Hz | |||||
| Current Sourcing | Micbias Mode 0 (CM=0.9V)(1) | 3 | mA | |||
| Micbias Mode 1 or Micbias Mode 2 (CM=0.9 V)(2) | 7 | mA | ||||
| Inline Resistance | Micbias Mode 3 | 63.6 | Ω | |||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT | ||||||
| Device Setup | Load = 10 kΩ (single-ended), 56 pF Input & Output CM=0.9 V DOSR = 128, MCLK=256* fs, Channel Gain = 0 dB, Processing Block = PRB_P1, Power Tune = PTM_P4 |
|||||
| Full scale output voltage (0dB) | 0.5 | VRMS | ||||
| SNR | Signal-to-noise ratio A-weighted(1) (2) | All zeros fed to DAC input | 85 | 101 | dB | |
| DR | Dynamic range, A-weighted (1) (2) | –60-dB 1-kHz input full-scale signal, Word length=20 bits | 101 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3dB full-scale, 1-kHz input signal | –88 | dB | ||
| DAC Gain Error | –3dB full-scale, 1-kHz input signal | 0.1 | dB | |||
| DAC Mute Attenuation | Mute | 119 | dB | |||
| DAC channel separation | –1 dB, 1kHz signal, between left and right Line out | 108 | dB | |||
| DAC PSRR | 100mVpp, 1kHz signal applied to AVDD_18, AVDDx_18 | 71 | dB | |||
| 100mVpp, 217Hz signal applied to AVDD_18, AVDDx_18 | 71 | dB | ||||
| AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT | ||||||
| Device Setup | Load = 10 kΩ (single-ended), 56pF Input & Output CM=0.75V; AVDD_18, AVDDx_18, HVDD_18=1.5V DOSR = 128 MCLK=256* fs Channel Gain = 0dB Processing Block = PRB_P1 Power Tune = PTM_P4 |
|||||
| Full scale output voltage (0dB) | 0.375 | VRMS | ||||
| SNR | Signal-to-noise ratio, A-weighted (1) (2) | All zeros fed to DAC input | 99 | dB | ||
| DR | Dynamic range, A-weighted (1) (2) | –60dB 1 kHz input full-scale signal, Word length=20 bits | 99 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3 dB full-scale, 1-kHz input signal | –88 | dB | ||
| AUDIO DAC – MONO DIFFERENTIAL LINE OUTPUT | ||||||
| Device Setup | Load = 10 kΩ (differential), 56pF Input & Output CM=0.9V, LOL signal routed to LOR amplifier DOSR = 128, MCLK=256* fs, Channel Gain = 0dB, Processing Block = PRB_P1, Power Tune = PTM_P4 |
|||||
| Full scale output voltage (0dB) | 1 | VRMS | ||||
| SNR | Signal-to-noise ratio A-weighted(1) (2) | All zeros fed to DAC input | 101 | dB | ||
| DR | Dynamic range, A-weighted (1) (2) | –60dB 1kHz input full-scale signal, | 101 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3dB full-scale, 1-kHz input signal | –86 | dB | ||
| DAC Gain Error | –3dB full-scale, 1-kHz input signal | 0.1 | dB | |||
| DAC Mute Attenuation | Mute | 97 | dB | |||
| DAC PSRR | 100mVpp, 1kHz signal applied to AVDD_18, AVDDx_18 | 62 | dB | |||
| 100mVpp, 217Hz signal applied to AVDD_18, AVDDx_18 | 63 | dB | ||||
| AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (GROUND-CENTERED CIRCUIT CONFIGURATION) | ||||||
| Device Setup | Load = 16Ω (single-ended), 56pF, Input CM=0.9V; DOSR = 128, MCLK=256* fs, Channel Gain = 0dB, Processing Block = PRB_P1, Power Tune = PTM_P3, Headphone Output Strength=100% |
|||||
| Output 1 | Output voltage | 0.5 | VRMS | |||
| SNR | Signal-to-noise ratio, A-weighted(1) (2) | All zeros fed to DAC input | 80 | 94 | dB | |
| DR | Dynamic range, A-weighted (1) (2) | –60dB 1 kHz input full-scale signal | 93 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3dB full-scale, 1-kHz input signal | –71 | –55 | dB | |
| DAC Gain Error | –3dB, 1kHz input full scale signal | –0.2 | dB | |||
| DAC Mute Attenuation | Mute | 92 | dB | |||
| DAC channel separation | –3dB, 1kHz signal, between left and right HP out | 83 | dB | |||
| DAC PSRR | 100mVpp, 1kHz signal applied to AVDD_18, AVDD1x_18 | 55 | dB | |||
| 100mVpp, 217Hz signal applied to AVDD_18, AVDD1x_18 | 55 | dB | ||||
| Power Delivered | THDN ≤ -40dB, Load = 16Ω | 15 | mW | |||
| Output 2 | Output voltage | Load = 16Ω (single-ended), Channel Gain = 5dB | 0.8 | VRMS | ||
| SNR | Signal-to-noise ratio, A-weighted(1) (2) | All zeros fed to DAC input, Load = 16Ω | 96 | dB | ||
| Power Delivered | THDN ≤ -40dB, Load = 16Ω | 24 | mW | |||
| Output 3 | Output voltage | Load = 32Ω (single-ended), Channel Gain = 5dB | 0.9 | VRMS | ||
| SNR | Signal-to-noise ratio, A-weighted(1) (2) | All zeros fed to DAC input, Load = 32Ω | 97 | dB | ||
| Power Delivered | THDN ≤ -40dB, Load = 32Ω | 22 | mW | |||
| AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (UNIPOLAR CIRCUIT CONFIGURATION) | ||||||
| Device Setup | Load = 16Ω (single-ended), 56pF Input & Output CM=0.9V, DOSR = 128, MCLK=256* fs, Channel Gain=0dB Processing Block = PRB_P1 Power Tune = PTM_P4 Headphone Output Control = 100% |
|||||
| Full scale output voltage (0dB) | 0.5 | VRMS | ||||
| SNR | Signal-to-noise ratio, A-weighted(1) (2) | All zeros fed to DAC input | 100 | dB | ||
| DR | Dynamic range, A-weighted (1) (2) | –60dB 1kHz input full-scale signal, Power Tune = PTM_P4 | 100 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3dB full-scale, 1-kHz input signal | –79 | dB | ||
| DAC Gain Error | –3dB, 1kHz input full scale signal | –0.2 | dB | |||
| DAC Mute Attenuation | Mute | 119 | dB | |||
| DAC channel separation | –1dB, 1kHz signal, between left and right HP out | 88 | dB | |||
| DAC PSRR | 100mVpp, 1kHz signal applied to AVDD_18, AVDD1x_18 | 64 | dB | |||
| 100mVpp, 217Hz signal applied to AVDD_18, AVDD1x_18 | 70 | dB | ||||
| Power Delivered | RL=16Ω THDN ≤ -40dB, Input CM=0.9V, Output CM=0.9V |
15 | mW | |||
| AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT (UNIPOLAR CIRCUIT CONFIGURATION) | ||||||
| Device Setup | Load = 16Ω (single-ended), 56pF, Input & Output CM=0.75V; AVDD_18, AVDDx_18, HVDD_18=1.5V, DOSR = 128, MCLK=256* fs, Channel Gain = 0dB, Processing Block = PRB_P1, Power Tune = PTM_P4 Headphone Output Control = 100% |
|||||
| Full scale output voltage (0dB) | 0.375 | VRMS | ||||
| SNR | Signal-to-noise ratio, A-weighted(1) (2) | All zeros fed to DAC input | 99 | dB | ||
| DR | Dynamic range, A-weighted (1) (2) | -60dB 1 kHz input full-scale signal | 99 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3dB full-scale, 1-kHz input signal | –77 | dB | ||
| AUDIO DAC – MONO DIFFERENTIAL RECEIVER OUTPUT | ||||||
| Device Setup | Load = 32 Ω (differential), 56pF, Output CM=1.65V, AVDDx_18=1.8V, DOSR = 128 MCLK=256* fs, Left DAC routed to LOL to RECP, LOL signal routed to LOR to RECM, Channel (Receiver Driver) Gain = 6dB for full scale output signal, Processing Block = PRB_P4, Power Tune = PTM_P4 |
|||||
| Full scale output voltage (0dB) | 2 | VRMS | ||||
| SNR | Signal-to-noise ratio, A-weighted(1) (2) | All zeros fed to DAC input | 90 | 99 | dB | |
| DR | Dynamic range, A-weighted (1) (2) | –60dB 1kHz input full-scale signal | 97 | dB | ||
| THD+N | Total Harmonic Distortion plus Noise | –3dB full-scale, 1-kHz input signal | –81 | dB | ||
| DAC PSRR | 100mVpp, 1kHz signal applied to AVDD_18, AVDD1x_18 | 56 | dB | |||
| 100mVpp, 217Hz signal applied to AVDD_18, AVDD1x_18 | 58 | dB | ||||
| Power Delivered | RL=32Ω THDN ≤ -40dB, Input CM=0.9V, Output CM=1.65V |
117 | mW | |||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8Ω (Differential), 56pF+33µH | |||||||
| Output voltage | SLVDD=SRVDD=3.6, BTL measurement, DAC input = 0dBFS, class-D gain = 12dB, THD+N ≤ –20dB, CM=0.9V | 2.67 | VRMS | ||||
| SNR | Signal-to-noise ratio | SLVDD=SRVDD=3.6V, BTL measurement, class-D gain = 6dB, measured as idle-channel noise, A-weighted (with respect to full-scale output value of 2 Vrms)(1) (2), CM=0.9V | 91 | dB | |||
| THD | Total harmonic distortion | SLVDD=SRVDD=3.6V, BTL measurement, DAC input = 0dBFS, class-D gain = 6dB, CM=0.9V | –66 | dB | |||
| THD+N | Total harmonic distortion + noise | SLVDD=SRVDD=3.6V, BTL measurement, DAC input = 0dBFS, class-D gain = 6dB, CM=0.9V | –66 | dB | |||
| PSRR | Power-supply rejection ratio | SLVDD=SRVDD=3.6V, BTL measurement, ripple on SPKVDD = 200 mVp-p at 1 kHz, CM=0.9V | 67 | dB | |||
| SLVDD=SRVDD=3.6V, BTL measurement, ripple on SPKVDD = 200 mVp-p at 217 Hz, CM=0.9V | 67 | dB | |||||
| Mute attenuation | Analog Mute Only | 102 | dB | ||||
| PO | Maximum output power | THD+N = 10%, f = 1 kHz, Class-D Gain = 12 dB, CM = 0.9 V, RL = 8 Ω | SLVDD = SRVDD = 3.6 V | 0.72 | W | ||
| SLVDD = SRVDD = 4.2 V | 1.00 | ||||||
| SLVDD = SRVDD = 5.5 V | 1.70 | ||||||
| THD+N = 1%, f = 1 kHz, Class-D Gain = 12 dB, CM = 0.9 V, RL = 8 Ω | SLVDD = SRVDD = 3.6 V | 0.58 | |||||
| SLVDD = SRVDD = 4.2 V | 0.80 | ||||||
| SLVDD = SRVDD = 5.5 V | 1.37 | ||||||
| DAC OUTPUT to CLASS-D SPEAKER OUTPUT; Load = 8 Ω (Differential), 56pF+33µH | |||||||
| Output voltage | SLVDD=SRVDD=5.0V, BTL measurement, DAC input = 0dBFS, class-D gain = 12dB, THD+N ≤ –20dB, CM=0.9V | 3.46 | VRMS | ||||
| SNR | Signal-to-noise ratio | SLVDD=SRVDD=5.0V, BTL measurement, class-D gain = 6dB, measured as idle-channel noise, A-weighted (with respect to full-scale output value of 2 Vrms)(1) (2) , CM=0.9V | 91 | ||||
| THD | Total harmonic distortion | SLVDD=SRVDD=5.0V, BTL measurement, DAC input = 0dBFS, class-D gain = 6dB, CM=0.9V | –70 | ||||
| THD+N | Total harmonic distortion + noise | SLVDD=SRVDD=5.0V, BTL measurement, DAC input = 0dBFS, class-D gain = 6dB, CM=0.9V | –70 | ||||
| PSRR | Power-supply rejection ratio | SLVDD=SRVDD=5.0V, BTL measurement, ripple on SPKVDD = 200mVp-p at 1kHz, CM=0.9V | 67 | ||||
| SLVDD=SRVDD=5.0V, BTL measurement, ripple on SPKVDD = 200 mVp-p at 217 Hz, CM=0.9V | 67 | ||||||
| Mute attenuation | Analog Mute Only | 102 | dB | ||||
| PO | Maximum output power | THD+N = 10%, f = 1 kHz, Class-D Gain = 12 dB, CM = 0.9 V, RL = 8 Ω | SLVDD = SRVDD = 5.0 V | 1.41 | W | ||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| REFERENCE - VREF_AUDIO | ||||||
| Reference Voltage Settings | CMMode = 0 (0.9V) | 0.9 | V | |||
| CMMode = 1 (0.75V) | 0.75 | |||||
| Reference Noise | CM=0.9V, A-weighted, 20Hz to 20kHz bandwidth, Cref = 1μF | 1.2 | μVRMS | |||
| Decoupling Capacitor | 1 | μF | ||||
| Bias Current | 99 | μA | ||||
| SHUTDOWN POWER | ||||||
| Device Setup | 粗調(diào) AVDD 電源被關(guān)閉,所有外部模擬電源供電并被設(shè)置為可用,無外部數(shù)字輸入被觸發(fā)時,寄存器值將被保留。 | |||||
| P(total)(1) | Sum of all supply currents, all supplies at 1.8 V except for SLVDD = SRVDD = SPK_V = 3.6 V and RECVDD_33 = AVDD3_33 = 3.3 V | 9.8 | μW | |||
| I(DVDD) | 2.6 | μA | ||||
| I(IOVDD) | 0.15 | μA | ||||
| I(AVDD1_18, AVDD2_18, AVDD4_18, AVDD_18, HVDD_18, CPVDD_18) | 1.15 | μA | ||||
| I(RECVDD_33, AVDD3_33) | 0.15 | μA | ||||
| I(SLVDD, SRVDD, SPK_V) | 0.5 | μA | ||||
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| LOGIC FAMILY (CMOS) | ||||||
| VIH | Logic Level | IIH = 5 μA, IOVDD > 1.65 V | 0.7 × IOVDD | V | ||
| IIH = 5 μA, 1.2 V ≤ IOVDD <1.65 V | 0.9 × IOVDD | V | ||||
| IIH = 5 μA, IOVDD < 1.2 V | IOVDD | V | ||||
| VIL | IIL = 5 μA, IOVDD > 1.65 V | –0.3 | 0.3 × IOVDD | V | ||
| IIL = 5 μA, 1.2 V ≤ IOVDD <1.65 V | 0.1 × IOVDD | V | ||||
| IIL = 5 μA, IOVDD < 1.2 V | 0 | V | ||||
| VOH | IOH = 3-mA load, IOVDD > 1.65 V | 0.8 × IOVDD | V | |||
| IOH = 1-mA load, IOVDD < 1.65 V | 0.8 × IOVDD | V | ||||
| VOL | IOL = 3-mA load, IOVDD > 1.65 V | 0.1 × IOVDD | V | |||
| IOL = 1-mA load, IOVDD < 1.65 V | 0.1 × IOVDD | V | ||||
| Capacitive Load | 10 | pF | ||||
| PARAMETER | IOVDD=1.8 V | IOVDD=3.3 V | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| td(WS) | WCLK delay | 22 | 20 | ns | ||
| td (DO-WS) | WCLK to DOUT delay (For LJF Mode only) | 22 | 20 | ns | ||
| td (DO-BCLK) | BCLK to DOUT delay | 22 | 20 | ns | ||
| ts(DI) | DIN setup | 4 | 4 | ns | ||
| th(DI) | DIN hold | 4 | 4 | ns | ||
| tr | BCLK Rise time | 10 | 8 | ns | ||
| tf | BCLK Fall time | 10 | 8 | ns | ||
Figure 1. I2S/LJF/RJF Timing in Master Mode
| PARAMETER | IOVDD=1.8 V | IOVDD=3.3 V | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| tH (BCLK) | BCLK high period | 30 | 30 | ns | ||
| tL (BCLK) | BCLK low period | 30 | 30 | ns | ||
| ts (WS) | WCLK setup | 4 | 4 | ns | ||
| th (WS) | WCLK hold | 4 | 4 | ns | ||
| td (DO-WS) | WCLK to DOUT delay (For LJF mode only) | 22 | 20 | ns | ||
| td (DO-BCLK) | BCLK to DOUT delay | 22 | 20 | ns | ||
| ts(DI) | DIN setup | 4 | 4 | ns | ||
| th(DI) | DIN hold | 4 | 4 | ns | ||
| tr | BCLK Rise time | 5 | 4 | ns | ||
| tf | BCLK Fall time | 5 | 4 | ns | ||
Figure 2. I2S/LJF/RJF Timing in Slave Mode
| PARAMETER | IOVDD=1.8 V | IOVDD=3.3 V | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| td (WS) | WCLK delay | 22 | 20 | ns | ||
| td (DO-BCLK) | BCLK to DOUT delay | 22 | 20 | ns | ||
| ts(DI) | DIN setup | 4 | 4 | ns | ||
| th(DI) | DIN hold | 4 | 4 | ns | ||
| tr | BCLK Rise time | 10 | 8 | ns | ||
| tf | BCLK Fall time | 10 | 8 | ns | ||
Figure 3. DSP/Mono PCM Timing in Master Mode
| PARAMETER | IOVDD=1.8 V | IOVDD=3.3 V | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| tH (BCLK) | BCLK high period | 30 | 30 | ns | ||
| tL (BCLK) | BCLK low period | 30 | 30 | ns | ||
| ts(WS) | WCLK setup | 4 | 4 | ns | ||
| th(WS) | WCLK hold | 4 | 4 | ns | ||
| td (DO-BCLK) | BCLK to DOUT delay | 22 | 20 | ns | ||
| ts(DI) | DIN setup | 5 | 5 | ns | ||
| th(DI) | DIN hold | 5 | 5 | ns | ||
| tr | BCLK Rise time | 5 | 4 | ns | ||
| tf | BCLK Fall time | 5 | 4 | ns | ||
Figure 4. DSP/Mono PCM Timing in Slave Mode
| PARAMETER | STANDARD-MODE | FAST-MODE | UNIT | |||||
|---|---|---|---|---|---|---|---|---|
| MIN | TYP | MAX | MIN | TYP | MAX | |||
| fSCL | SCL clock frequency | 0 | 100 | 0 | 400 | kHz | ||
| tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 4.0 | 0.8 | μs | ||||
| tLOW | LOW period of the SCL clock | 4.7 | 1.3 | μs | ||||
| tHIGH | HIGH period of the SCL clock | 4.0 | 0.6 | μs | ||||
| tSU;STA | Setup time for a repeated START condition | 4.7 | 0.8 | μs | ||||
| tHD;DAT | Data hold time: For I2C bus devices | 0 | 3.45 | 0 | 0.9 | μs | ||
| tSU;DAT | Data set-up time | 250 | 100 | ns | ||||
| tr | SDA and SCL Rise Time | 1000 | 20+0.1Cb | 300 | ns | |||
| tf | SDA and SCL Fall Time | 300 | 20+0.1Cb | 300 | ns | |||
| tSU;STO | Set-up time for STOP condition | 4.0 | 0.8 | μs | ||||
| tBUF | Bus free time between a STOP and START condition | 4.7 | 1.3 | μs | ||||
| Cb | Capacitive load for each bus line | 400 | 400 | pF | ||||
Figure 5. I2C Interface Timing Diagram
| PARAMETER | IOVDD=1.8 V | IOVDD=3.3 V | UNIT | |||||
|---|---|---|---|---|---|---|---|---|
| MIN | TYP | MAX | MIN | TYP | MAX | |||
| tsck | SCLK Period(1) | 50 | 40 | ns | ||||
| tsckh | SCLK Pulse width High | 25 | 20 | ns | ||||
| tsckl | SCLK Pulse width Low | 25 | 20 | ns | ||||
| tlead | Enable Lead Time | 25 | 20 | ns | ||||
| ttrail | Enable Trail Time | 25 | 20 | ns | ||||
| td;seqxfr | Sequential Transfer Delay | 25 | 20 | ns | ||||
| ta | Slave DOUT (MISO) access time | 25 | 20 | ns | ||||
| tdis | Slave DOUT (MISO) disable time | 25 | 20 | ns | ||||
| tsu | DIN (MOSI) data setup time | 8 | 8 | ns | ||||
| th;DIN | DIN (MOSI) data hold time | 8 | 8 | ns | ||||
| tv;DOUT | DOUT (MISO) data valid time | 20 | 14 | ns | ||||
| tr | SCLK Rise Time | 4 | 4 | ns | ||||
| tf | SCLK Fall Time | 4 | 4 | ns | ||||
Figure 6. SPI Timing Diagram
Figure 7. ADC SNR vs Channel Gain
Figure 9. ADC Differential Input to ADC FFT at -3 DBR vs Frequency
Figure 8. ADC Single Ended Input to ADC Fft at -3 DBR vs Frequency
Figure 10. DAC to Line Output FFT Amplitude at -3 dBFS vs Frequency 10-kΩ Load
Figure 12. DAC to Headphone Output (GCHP) FFT Amplitude at -3 dBFS vs Frequency
Figure 14. Total Harmonic Distortion+Noise vs Headphone (GCHP) Output Power
Figure 16. Differential Receiver SNR and Output Power vs Output Common Mode Setting 32-Ω Load
Figure 11. DAC to Headphone Output (GCHP) FFT Amplitude at -3 dBFS vs Frequency
Figure 13. DAC to Differential Receiver Output FFT Amplitude at -3 dBFS vs Frequency
Figure 15. Total Harmonic Distortion+Noise vs Differential Receiver Output Power
Figure 17. Total Harmonic Distortion + Noise vs Output Power with
Figure 18. Total Harmonic Distortion + Noise vs Output Power with
Figure 19. MICBIAS Mode 2, CM = 0.9V, AVDD3_33 OP STAGE vs MICBIAS Load Current