8.3.1 Analog MUX

The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then sampled and converted in the same manner as the external analog inputs. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling.

8.3.2 Reference

An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive supply or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or lower than REF–.

Figure 39. Reference Block Diagram

8.4.1 Converter Operation

The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2) the sampling cycle and 3) the conversion cycle. The first two are partially overlapped.

8.4.2 Data I/O Cycle

The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending on the selected output data length. During the I/O cycle, the following two operations take place simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided to DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. DATA INPUT is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK.

8.4.3 Sampling Cycle

During the sampling cycle, one of the analog inputs is internally connected to the capacitor array of the converter to store the analog input signal. The converter starts sampling the selected input immediately after the four address/command bits have been clocked into the input data register. Sampling starts on the fourth falling edge of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of the I/O CLOCK depending on the data-length selection.

After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence of external digital noise.

8.4.4 Conversion Cycle

A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (approximately Í25 ns) to start the OSC. During the conversion period, the device performs a successive-approximation conversion on the analog input voltage.

EOC goes low at the start of the conversion cycle and goes high when the conversion is complete and the output data register is latched. After EOC goes low, the analog input can be changed without affecting the conversion result. Because the delay from the falling edge of the last I/O CLOCK to the falling edge of EOC is fixed, any time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.

8.4.5 Power Up and Initialization

After power up, CS must be taken from high to low to begin an I/O cycle. The EOC pin is initially high, and the configuration register is set to all zeroes. The contents of the output data register are random, and the first conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling.

8.4.6 Data Input

The data input is internally connected to an 8-bit serial-input address and control register. The register defines the operation of the converter and the output data length. The host provides the input data byte with the MSB first. Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data input-register format).

8.4.7 Data Input—Address/Command Bits

The four MSBs (D7–D4) of the input data register are the address or command. These can be used to address one of the 11 input channels, address one of three reference-test voltages, or activate software power-down mode. All address/command bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. They also have access to CFGR1 except for command 1111b, which is reserved.

8.4.8 Data Output Length

CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be selected. Because the converter has 12-bit resolution, a data length of 12 bits is suggested.

With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.

With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current I/O cycle.

With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the current I/O cycle.

Because the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data format is selected to be least significant bit first, because at the time the data length change becomes effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation, when different data lengths are required within an application and the data length is changed between two conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first format.

8.4.9 LSB Out First

D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to another, the current I/O cycle is never disrupted.

8.4.10 Bipolar Output Format

D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an input voltage equal to or less than V_REF– is a code with all zeros (000 . . . 0) and the conversion result of an input voltage equal to or greater than V_REF+ is a code of all ones (111 . . . 1). The conversion result of (V_REF+ + V_REF–)/2 is a code of a one followed by zeros (100 ...0).

When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion of an input voltage equal to or less than V_REF– is a code of a one followed by zeros (100 . . . 0), and the conversion of an input voltage equal to or greater than V_REF+ is a code of a zero followed by all ones (011 . . . 1). The conversion result of (V_REF+ + V_REF–)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other’s complement.

Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the current I/O cycle is not affected.

8.4.11 EOC Output

Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes low, the analog input signal can be changed without affecting the conversion result.

The EOC signal goes high again after the conversion is completed and the conversion result is latched into the output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins. On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the falling edge of CS.

8.4.12 Chip-Select Input (CS)

CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data transfer of several devices sharing the same bus.

When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is inhibited, thus preventing any further change in the internal state.

When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low) for a minimum time before a new I/O cycle can start.

CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough before the end of the current conversion cycle, the previous conversion result is saved in the internal output buffer and shifted out during the next I/O cycle.

When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs on DATA OUT on the rising edge of EOC.

When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in the serial conversion result until the required number of bits has been output.

8.4.13 Power-Down Features

When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles, the software power-down mode is selected. Software power down is activated on the falling edge of the fourth I/O CLOCK pulse.

During software power-down, all internal circuitry is put in a low-current standby mode. No conversions is performed. The internal output buffer keeps the previous conversion cycle data results, provided that all digital inputs are greater than VC_C – 0.5 V or less than 0.5 V. The I/O logic remains active so the current I/O cycle must be completed even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The device remains in the software power-down mode until a valid input address (other than command 1110b or 1111b) is clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted out during the next I/O cycle.

The ADC also has an auto power-down mode. This is transparent to users. The ADC gets into auto power-down within 1 I/O CLOCK cycle after the conversion is complete and resumes, with a small delay, after an active CS is sent to the ADC. The resumption is fast enough to be used between cycles.