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SLES032E June 2002 – September 2014 THS8200

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PFP|80
- MPQF049B

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

PFP|80
- PPTD014N

訂購(gòu)信息

4 Specifications

4.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
	Supply voltage range	AV_DD to AV_SS, VDD_IO to GND_IO	−0.5	4.5	V
	Supply voltage range	DV_DD to DV_SS, VDD_DLL to DVSS	−0.5	2.5	V
	Digital input voltage range to DV_SS		−0.5	VDD_IO + 0.5	V
T_A	Operating free-air temperature range		0	70	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 Handling Ratings

		MIN	MAX	UNIT
T_stg	Storage temperature range	–55	150	°C

4.3 Recommended Operating Conditions

over operating free-air temperature range, T_A

			MIN	NOM	MAX	UNIT
POWER SUPPLY
	Supply voltage	AV_DD	3	3.3	3.6	V
		DV_DD, VDD_DLL	1.65	1.8	2
		VDD_IO	1.65	1.8 or 3.3	3.6
DIGITAL AND REFERENCE INPUTS
V_IH	High-level input voltage	VDD_IO = 1.8 V	0.95		VDD_IO	V
V_IH	High-level input voltage	VDD_IO = 3.3 V	2.3		VDD_IO	V
V_IL	Low-level input voltage	VDD_IO = 1.8 V	DV_SS		0.4	V
V_IL	Low-level input voltage	VDD_IO = 3.3 V	DV_SS		1.15	V
f_clk	Clock frequency		10		205	MHz
t_w(CLKH)	Pulse duration, clock high		40%		60%
t_w(CLKL)	Pulse duration, clock low		40%		60%
R_FS	FSADJ resistor	V_OC = 700 mV		2.99		kΩ
R_FS	FSADJ resistor	V_OC = 1 V		2.08		kΩ

4.4 Power Consumption Summary

Table 4-1 Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels

f (MHz)	POWER (mW), DLL BYPASSED	POWER (mW), DLL USED	IAVDD (mA)	IDVDD (mA)	IVDD_IO (mA)	IVDD_DLL (mA)
20	329.91	332.88	93.2	10.4	1.1	0.9
30	338.52	351.72	93.2	15	1.2	4
80	382.47	399.63	93.2	38.5	1.7	5.2
160	450.51		93.2	75.2	2.3
200	476.01		93.2	89	2.5

Figure 4-1 Power vs Frequency

Table 4-2 Power for 700-mV DAC Output Compliance + 350-mV Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels

f (MHz)	POWER (mW), DLL BYPASSED	POWER (mW), DLL USED	IAVDD (mA)	IDVDD (mA)	IVDD_IO (mA)	IVDD_DLL (mA)
20	328.26	331.23	93.2	10.4	1.1	0.9
30	336.72	349.92	93.2	15	1.2	4
80	379.92	397.08	93.2	38.5	1.7	5.2
160	447.06		93.2	75.2	2.3
200	472.26		93.2	89	2.5

Figure 4-2 Power vs Frequency

Table 4-3 Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 3.3 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels

f (MHz)	POWER (mW), DLL BYPASSED	POWER (mW), DLL USED	IAVDD (mA)	IDVDD (mA)	IVDD_IO (mA)	IVDD_DLL (mA)
20	556.95	559.92	162	10.4	1.1	0.9
30	565.56	578.76	162	15	1.2	4
80	609.51	626.67	162	38.5	1.7	5.2
160	677.55		162	75.2	2.3
200	703.05		162	89	2.5

Figure 4-3 Power vs Frequency

Table 4-4 Power for 1.25-V Output Compliance Without Bias at AVDD = 3.3 V, DVDD = 1.8 V, VDD_IO = 1.8 V, VDD_DLL = 3.3 V, 1-MHz Tone on All Channels

f (MHz)	POWER (mW), DLL BYPASSED	POWER (mW), DLL USED	IAVDD (mA)	IDVDD (mA)	IVDD_IO (mA)	IVDD_DLL (mA)
20	555.30	558.27	162	10.4	1.1	0.9
30	563.76	576.96	162	15	1.2	4
80	606.96	624.12	162	38.5	1.7	5.2
160	674.10		162	75.2	2.3
200	699.30		162	89	2.5

Figure 4-4 Power vs Frequency

4.5 Power Supply

1-MHz FS ramp simultaneously applied to all three channels
over recommended operating conditions with f_CLK = 205 MHz, R_FS = R_FS(nom) (unless otherwise noted)

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
IAV_DD	Operating analog supply current	AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V, VDD_IO = 3.3 V, CLK = 80 MHz	Video + no bias (700 mV)	94	98	mA
			Video + bias (1.05 V)	94	98
			Generic + no bias (1.25 V)	162	170
		AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V (DLL bypassed), VDD_IO = 1.8 V, CLK = 200 MHz	Video + no bias (700 mV)	94	98
			Video + bias (1.05 V)	94	98
			Generic + no bias (1.25 V)	162	170
IDV_DD	Operating digital supply current	AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V, VDD_IO = 3.3 V, CLK = 80 MHz	Video + no bias (700 mV)	38	45	mA
			Video + bias (1.05 V)	38	45
			Generic + no bias (1.25 V)	38	45
		AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V (DLL bypassed), VDD_IO = 1.8 V, CLK = 200 MHz	Video + no bias (700 mV)	89	95
			Video + bias (1.05 V)	89	95
			Generic + no bias (1.25 V)	89	95
IVDD_IO	Operating I/O supply current	AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V, VDD_IO = 3.3 V, CLK = 80 MHz	Video + no bias (700 mV)	1.7	2.2	mA
			Video + bias (1.05 V)	1.7	2.2
			Generic + no bias (1.25 V)	1.7	2.2
		AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V (DLL bypassed), VDD_IO = 1.8 V, CLK = 200 MHz	Video + no bias (700 mV)	1.7	2.2
			Video + bias (1.05 V)	1.7	2.2
			Generic + no bias (1.25 V)	1.7	2.2
IVDD_DLL	Operating DLL supply current	AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V, VDD_IO = 3.3 V, CLK = 80 MHz	Video + no bias (700 mV)	4.9	5.6	mA
			Video + bias (1.05 V)	4.9	5.6
			Generic + no bias (1.25 V)	4.9	5.6
		AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V (DLL bypassed), VDD_IO = 1.8 V, CLK = 200 MHz	Video + no bias (700 mV)	4.9	5.6
			Video + bias (1.05 V)	4.9	5.6
			Generic + no bias (1.25 V)	4.9	5.6
P_D	Power disspiation	AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V, VDD_IO = 3.3 V, CLK = 80 MHz	Video + no bias (700 mV)	398	430	mW
			Video + bias (1.05 V)	398	430
			Generic + no bias (1.25 V)	641	660
		AV_DD = 3.3 V, DV_DD = 1.8 V, VDD_DLL = 1.8 V (DLL bypassed), VDD_IO = 1.8 V, CLK = 200 MHz	Video + no bias (700 mV)	489	500
			Video + bias (1.05 V)	489	500
			Generic + no bias (1.25 V)	700	735

4.6 Digital Inputs, DC Characteristics

over recommended operating conditions with f_CLK = 205 MHz, R_FS = R_FS(nom) (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_IH	High-level input current	VDD_IO = 3.3 V, Digital inputs and CLK at 0 V for I_IL, Digital inputs and CLK at 3.6 V for I_IH			1	µA
I_IL	Low-level input current				−1	µA
I_IL(CLK)	Low-level input current, CLK				1	µA
I_IH(CLK)	High-level input current, CLK				−1	µA
C_I	Input capacitance	T_A = 25°C		5		pF
t_s	GY, RCr, BCb data inputs setup time	VDD_IO = 1.8 V	1.5			ns
t_s	GY, RCr, BCb data inputs setup time	VDD_IO = 3.3 V	1.5			ns
t_H	GY, RCr, BCb data inputs hold time	VDD_IO = 1.8 V	0.5			ns
t_H	GY, RCr, BCb data inputs hold time	VDD_IO = 3.3 V	0.5			ns
t_s	HS_IN, VS_IN, FID inputs setup time	VDD_IO = 3.3 V ⁽¹⁾	1.5			ns
t_H	HS_IN, VS_IN, FID inputs hold time	VDD_IO = 3.3 V ⁽¹⁾	0.5			ns
t_d(D)	Digital process delay ⁽²⁾	10-bit/20-bit 4:2:2 with CSM, CSC, 2x interpolation active		73 ⁽³⁾		pixels
		30-bit 4:4:4		33 ⁽³⁾
		VESA clock mode (DLL, CSM, CSC, FIRs bypassed)		9

4.7 Analog (DAC) Outputs

over recommended operating conditions with f_CLK = 205 MHz, R_FS = R_FS(nom) (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
	DAC resolution			10 (11 bit internal)	10 (11 bit internal)		bits
INL	Integral nonlinearity	Best-fit VDD_IO = 3.3 V, CLK = 500 kHz	Video (0.7 + 0.35 V bias)		+0.5/-1.2	+2/-2	LSB
INL	Integral nonlinearity	Best-fit VDD_IO = 3.3 V, CLK = 500 kHz	Generic (1.25 + 0 V bias)		+1/-2.1	+5/-5	LSB
DNL	Differential nonlinearity	VDD_IO = 3.3 V, CLK = 500 kHz	Video (0.7 + 0.35 V bias)		+0.2/−0.3	+1/−1	LSB
DNL	Differential nonlinearity	VDD_IO = 3.3 V, CLK = 500 kHz	Generic (1.25 + 0 V bias)		+0.3/-0.5	+1/−1	LSB
PSRR	Power supply ripple rejection ratio of DAC output (full scale)	f = dc to 100 kHz ⁽⁴⁾		40	42		dB
XTALK	Crosstalk between channels ⁽⁵⁾	CLK = 205 MHz, -1 dB sine wave applied to active channels, offset bias applied to all channels when turned on, 37.5-Ω load on all channels	1-MHz sine wave, offset bias off		49		dB
			1-MHz sine wave, offset bias on		42
			10-MHz sine wave, offset bias off		49
			10-MHz sine wave, offset bias on		42
			30-MHz sine wave, offset bias off		48
			30-MHz sine wave, offset bias on		40.5
K_IMBAL	Imbalance between DACs	CLK = 80 MHz ⁽⁶⁾				±2%
V_OC	DAC output compliance voltage (video only)	R_L = 37.5 Ω ⁽⁷⁾	Video mode (bias offset can be added)		0.7	0.72	V
V_OC	DAC output compliance voltage (video only)	R_L = 37.5 Ω ⁽⁷⁾	Generic mode (bias offset cannot be added)		1.25	1.3	V
C_O	DAC output capacitance (pin capacitance)				5		pF
t_ri	DAC output current rise time	10 to 90% of full scale, CLK = 80 MHz			3.5	4.2	ns
t_fi	DAC output current fall time	10 to 90% of full scale, CLK = 80 MHz			3.5	4.2	ns
t_d	Analog output delay	Measured from falling edge of CLKIN to 50% of full-scale transition ⁽⁸⁾			6.5		ns
t_sa	Analog output settling time	Measured from 50% of full scale transition on output to output settling, within 2% ⁽⁹⁾			6.6		ns
SFDR	Spurious-free dynamic range	1 MHz, −1 dB FS digital sine input			-55		dB
SFDR	Spurious-free dynamic range	10 MHz, −1 dB FS digital sine input			-43		dB
BW	Bandwidth (3 dB)				90		MHz
E_glitch	Glitch energy	Full-scale code transition at 205 MSPS			25		pVs

(1) The HS_IN, VS_IN, and FID input setup and hold times are valid for 3.3-V I/O operation only. These sync inputs are not recommended for use with 1.8-V I/O logic levels.

(2) Defined as the delay on Y pixel data, starting from the rising edge of CLKIN, until the clock period.

(3) CSC contribution: 8 pixels, CSM contribution: 1 pixel, 2x interpolation filter contribution: 18 pixels

(4) PSRR is defined as 20 × log(ripple voltage at DAC output / ripple voltage at AVDD input). Limits from characterization only.

(5) Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limit from characterization only.

(6) The imbalance between DACs applies to all possible pairs of the three DACs.

(7) Nominal values at R_FS = R_FS(nom). Limit from characterization only. Excludes bias offset.

(8) This value excludes the digital process delay, t_D(D). Limit from characterization only. Data is clocked in on the rising edge of CLKIN. Analog outputs become available on the falling edge of CLKIN.

(9) Limit from characterization only.

4.8 Nonlinearity

4.8.1 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV Without Bias

Figure 4-5 Integral Nonlinearity vs Code

Figure 4-6 Differential Nonlinearity vs Code

4.8.2 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV + 350-mV Bias

Figure 4-7 Integral Nonlinearity vs Code

Figure 4-8 Differential Nonlinearity vs Code

4.8.3 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 1.25 V Without Bias

Figure 4-9 Integral Nonlinearity vs Code

Figure 4-10 Differential Nonlinearity vs Code

4.9 Analog Output Bandwidth (sinx/x corrected) at f_S = 205 MSPS

Figure 4-11 Amplitude vs Output Frequency

4.10 Output Compliance vs Full-Scale Adjustment Resistor Value

Figure 4-12 Output Voltage vs Full-Scale Resistance

4.11 Vertical Sync of the HDTV 1080I Format Preset in First and Second Field, and Horizontal Line Waveform Detail

Figure 4-13 THS8200 Output Waveforms for 1080I: Vertical Blanking in First and Second Fields, and Active Video