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ZHCSGC4D March 2016 – April 2021 TCAN1051-Q1 , TCAN1051G-Q1 , TCAN1051GV-Q1 , TCAN1051H-Q1 , TCAN1051HG-Q1 , TCAN1051HGV-Q1 , TCAN1051HV-Q1 , TCAN1051V-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

D|8
- MSOI002K
DRB|8
- MPDS118K

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

DRB|8
- QFND562A

訂購信息

6.8 Switching Characteristics

Over recommended operating conditions with T_A = -55°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
Device Switching Characteristics
t_PROP(LOOP1)	Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant	See Figure 7-4, S = 0 V, R_L = 60 ?, C_L = 100 pF, C_L(RXD) = 15 pF		100	160	ns
t_PROP(LOOP2)	Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive			110	175	ns
t_MODE	Mode change time, from Normal to Silent or from Silent to Normal	See Figure 7-3		1	10	μs
Driver Switching Characteristics
t_pHR	Propagation delay time, high TXD to driver recessive (dominant to recessive)	See Figure 7-1, S = 0 V, R_L = 60 ?, C_L = 100 pF, R_CM = open		75		ns
t_pLD	Propagation delay time, low TXD to driver dominant (recessive to dominant)			55
t_sk(p)	Pulse skew (\|t_pHR - t_pLD\|)			20
t_R	Differential output signal rise time			45
t_F	Differential output signal fall time			45
SR	Differential output slew rate, dominant-to-recessive transition				70	V/μs
t_{TXD_DTO}	Dominant timeout	See Figure 7-6, S = 0 V, R_L = 60 ?, C_L = open	1.2		3.8	ms
Receiver Switching Characteristics
t_pRH	Propagation delay time, bus recessive input to high output (Dominant to Recessive)	See Figure 7-2, S = 0 V, C_L(RXD) = 15 pF		65		ns
t_pDL	Propagation delay time, bus dominant input to low output (Recessive to Dominant)			50		ns
t_R	RXD Output signal rise time			10		ns
t_F	RXD Output signal fall time			10		ns
FD Timing Parameters
t_BIT(BUS)	Bit time on CAN bus output pins with t_BIT(TXD) = 500 ns, all devices	See Figure 7-5 , S = 0 V, R_L = 60 ?, C_L = 100 pF, C_L(RXD) = 15 pF, Δt_REC = t_BIT(RXD) - t_BIT(BUS)	435		530	ns
t_BIT(BUS)	Bit time on CAN bus output pins with t_BIT(TXD) = 200 ns, G device variants only		155		210
t_BIT(RXD)	Bit time on RXD output pins with t_BIT(TXD) = 500 ns, all devices		400		550
t_BIT(RXD)	Bit time on RXD output pins with t_BIT(TXD) = 200 ns, G device variants only		120		220
Δt_REC	Receiver timing symmetry with t_BIT(TXD) = 500 ns, all devices		-65		40
Δt_REC	Receiver timing symmetry with t_BIT(TXD) = 200 ns, G device variants only		-45		15

(1) All typical values are at 25°C and supply voltages of V_CC = 5 V and V_IO = 5 V (if applicable), R_L = 60 ?