SCAS568N March 1996 – September 2014 SN74LVCH16373A
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Simplified Schematic
- 5 Revision History
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 Handling Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements, -40°C to 85°C
- 7.7 Timing Requirements, -40°C to 125°C
- 7.8 Switching Characteristics, -40°C to 85°C
- 7.9 Switching Characteristics, -40°C to 125°C
- 7.10 Operating Characteristics
- 7.11 Typical Characteristics
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DGG|48
- DL|48
- DGV|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
1 Features
- Member of the Texas Instruments Widebus™ Family
- Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C - Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
- Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Bus Hold on Data Inputs Eliminates the Need for External Pull-up or Pull-down Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
3 Description
This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74LVCH16373A | SSOP (48) | 15.80 mm × 7.50 mm |
| TSSOP (48) | 12.50 mm × 6.10 mm | |
| TVSOP (48) | 9.70 mm × 4.40 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
4 Simplified Schematic
