ZHCSKK0F December 2019 – December 2021 SN74HCS595-Q1
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- BQB|16
訂購信息
5 Pin Configuration and Functions
Figure 5-1 D, PW, or DYY Package16-Pin SOIC, TSSOP, or SOT
Top View
Figure 5-2 WBQB (Preview) or BQB
Package16-Pin WQFN
Transparent Top View
Table 5-1 Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| QB | 1 | Output | QB output |
| QC | 2 | Output | QC output |
| QD | 3 | Output | QD output |
| QE | 4 | Output | QE output |
| QF | 5 | Output | QF output |
| QG | 6 | Output | QG output |
| QH | 7 | Output | QH output |
| GND | 8 | — | Ground |
| QH' | 9 | Output | Serial output, can be used for cascading |
| SRCLR | 10 | Input | Shift register clear, active low |
| SRCLK | 11 | Input | Shift register clock, rising edge triggered |
| RCLK | 12 | Input | Output register clock, rising edge triggered |
| OE | 13 | Input | Output Enable, active low |
| SER | 14 | Input | Serial input |
| QA | 15 | Output | QA output |
| VCC | 16 | — | Positive supply |
| Thermal Pad(1) | — | The thermal pad can be connect to GND or left floating. Do not connect to any other signal or supply. | |
(1) BQB and WBQB package only.