SCPS145B December 2007 – February 2016 P82B715
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據 (封裝 | 引腳)
散熱焊盤機械數(shù)據 (封裝 | 引腳)
訂購信息
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VCC | Supply voltage | –0.3 | 12 | V | |
| Vb | I2C bus voltage | Sx or Sy | 0 | VCC | V |
| Buffered bus voltage | Lx or Ly | 0 | VCC | ||
| IO | Continuous output current | Sx or Sy | 60 | mA | |
| Lx or Ly | 60 | ||||
| ICC | Continuous current through VCC or GND | 60 | mA | ||
| Tstg | Storage temperature | –55 | 125 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
| Machine model (MM) | ±400 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VCC | Supply voltage(1) | 4.5 | 12 | V | |
| TA | Operating free-air temperature | –40 | 85 | °C | |
(1) Operation with reduced performance is possible down to 3 V. Typical static sinking performance is not degraded at 3 V, but the dynamic sink currents while the output is being driven through VCC/2 are reduced and can increase fall times. Timing-critical designs should accommodate the specified minimums.
6.4 Thermal Information
| THERMAL METRIC(1) | P82B715 | UNIT | ||
|---|---|---|---|---|
| D (SOIC) | P (PDIP) | |||
| 8 PINS | 8 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 105.3 | 48.9 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 51.1 | 38.1 | °C/W |
| RθJB | Junction-to-board thermal resistance | 46.2 | 26.1 | °C/W |
| ψJT | Junction-to-top characterization parameter | 8.5 | 15.4 | °C/W |
| ψJB | Junction-to-board characterization parameter | 45.6 | 26 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
VCC = 5 V, TA = 25°C, voltages are specified with respect to GND (unless otherwise specified)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| ICC | Quiescent supply current | Sx = Sy = VCC | 14 | mA | |||
| VCC = 12 V | 15 | ||||||
| Both I2C inputs low, Both buffered outputs sinking 30 mA |
22 | ||||||
| IIOS | Output sink current on I2C bus | Sx, Sy | VCC > 3 V, VSx, VSy (low) = 0.4 V, VLx, VLy (low) on buffered bus = 0.3 V, ILx, ILy = –3 mA (1) |
2.6 | mA | ||
| IIOL | Output sink current on buffered bus | Lx, Ly | VLx, VLy (low) = 0.4 V, VSx, VSy (low) on I2C bus = 0.3 V |
30 | mA | ||
| 3 V < VCC < 4.5 V, VLx, VLy (low) = 0.4 V to 1.5 V, ISx, ISy sinking on I2C bus < –4 mA |
24 | ||||||
| 3 V < VCC < 4.5 V, VLx, VLy (low) = 1.5 V to VCC, ISx, ISy sinking on I2C bus = –7 mA |
24 | ||||||
| II | Input current from I2C bus | Sx, Sy | ILx, ILy sink on buffered bus = 30 mA | –3.2 | mA | ||
| Input current from buffered bus(1) | Lx, Ly | VCC > 3 V, ISx, ISy sink on I2C bus = 3 mA(1) |
–3 | ||||
| Leakage current on buffered bus | VCC = 3 V to 12 V, VLx, VLy = VCC, VSx, VSy = VCC |
200 | μA | ||||
| Zin/Zout | Input/output impedance | VSx < VLx, Buffer is active | 8 | 10 | 13 | ||
(1) Buffer is passive in this test. The Sx/Sy sink current flows through an internal resistor to the driver connected at the Lx/Ly I/O.
6.6 Switching Characteristics
VCC = 5 V, TA = 25°C, no capacitive loads, voltages are specified with respect to GND (unless otherwise specified)| PARAMETER | TEST CONDITIONS | FROM (INPUT) |
TO (OUTPUT) |
MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|---|---|
| BUFFER DELAY TIMES | ||||||||
| trise/fall | Delay time to VLx voltage crossing VCC/2 for input drive current step ISx at Sx(1) (see Figure 2) | RLx pullup = 270 Ω | ISx
ISy |
VLx
VLy |
250 | ns | ||
| Buffer delay time, switching edges between VLx input and VSx output(2) |
RLx pullup = 4700 Ω | VLx
VLy |
VSx
VSy |
0 | ns | |||
(1) A conventional input-output delay is not observed in the Sx/Lx voltage waveforms, because the input and output pins are internally tied with a 30-Ω resistor so they show equal logic voltage levels to within 100 mV. When connected in an I2C system, an Sx/Sy input pin cannot rise/fall until the buffered bus load at the output pin has been driven by the internal amplifier. This test measures the bus propagation delay caused to falling or rising voltages at the Lx/Ly output (as well as the Sx/Sy input) by the amplifier’s response time. The figure given is measured with a drive current as shown in Figure 2. Because this is a dynamic bus test in which a corresponding bus driving IC has an output voltage well above 0.4 V, 6 mA is used instead of the static 3 mA.
(2) The signal path Lx to Sx and Ly to Sy is passive through the internal 30-Ω resistor. There is no amplifier involved and essentially no signal propagation delay.
6.7 Typical Characteristics
