ZHCSGL2E December 2016 – December 2023 LMK62A2-100M , LMK62A2-150M , LMK62A2-156M , LMK62A2-200M , LMK62A2-266M , LMK62E0-156M , LMK62E2-100M , LMK62E2-156M , LMK62I0-100M , LMK62I0-156M
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics - Power Supply
- 5.6 LVPECL Output Characteristics
- 5.7 LVDS Output Characteristics
- 5.8 HCSL Output Characteristics
- 5.9 OE Input Characteristics
- 5.10 Frequency Tolerance Characteristics
- 5.11 Power-On/Reset Characteristics (VDD)
- 5.12 PSRR Characteristics
- 5.13 PLL Clock Output Jitter Characteristics
- 5.14 Additional Reliability and Qualification
- 6 Parameter Measurement Information
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- SIA|6
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
4 Pin Configuration and Functions
Figure 4-1 SIA Package6-pin QFMTop ViewTable 4-1 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| POWER | |||
| GND | 3 | Ground | Device ground |
| VDD | 6 | Analog | 3.3-V power supply |
| OUTPUT BLOCK | |||
| OUTP | 4 | Universal | Differential output pair (LVPECL, LVDS or HCSL). |
| OUTN | 5 | ||
| DIGITAL CONTROL / INTERFACES | |||
| NC | 2 | N/A | No connect |
| OE | 1 | LVCMOS | Output enable (internal pulldown). When set to low,
output pair is disabled and set at high impedance. The recommended external pullup resistor value is 10 kΩ. |