ZHCSOY4B september 2021 – june 2023 LMK1D2102 , LMK1D2104
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Application and Implementation
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHD|28
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHD|28
訂購(gòu)信息
9.4.2 Input Termination
The LMK1D210x inputs can be interfaced with LVDS, LVPECL, HCSL or LVCMOS drivers.
LVDS drivers can be connected to LMK1D210x inputs with DC- and AC-coupling as shown Figure 9-3 and Figure 9-4 (respectively).
Figure 9-3 LVDS
Clock Driver Connected to LMK1D210x Input (DC-Coupled)
Figure 9-4 LVDS
Clock Driver Connected to LMK1D210x Input (AC-Coupled)Figure 9-5 shows how to connect LVPECL inputs to the LMK1D210x. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP.
Figure 9-5 LVPECL
Clock Driver Connected to LMK1D210x InputFigure 9-6 illustrates how to couple a LVCMOS clock input to the LMK1D210x directly.
Figure 9-6 1.8-V/2.5-V/3.3-V LVCMOS Clock Driver Connected to LMK1D210x InputUnused inputs can be left floating thus reducing the need for additional components.