ZHCSEU0A November 2015 – December 2015 LM5109B-Q1
PRODUCTION DATA.
The LM5109B-Q1 is a cost-effective, high voltage gate driver designed to drive both the high-side and the low-side N-channel FETs in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with TTL/CMOS compatible input thresholds. The floating high-side driver is capable of working with HB voltage up to 108 V. An external high voltage diode must be provided to charge high side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high side gate driver. Under-voltage lockout (UVLO) is provided on both the low side and the high side power rails.
Both top and bottom drivers include UVLO protection circuitry which monitors the supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each output until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents chattering during supply voltage variations. When the supply voltage is applied to the VDD pin of the LM5109B-Q1, the top and bottom gates are held low until VDD exceeds the UVLO threshold, typically about 6.7 V. Any UVLO condition on the bootstrap capacitor (VHB–HS) will only disable the high- side output (HO).
| Condition (VHB-HS>VHBR for all case below) | HI | LI | HO | LO |
|---|---|---|---|---|
| VDD-VSS < VDDR during device start-up | H | L | L | L |
| VDD-VSS < VDDR during device start-up | L | H | L | L |
| VDD-VSS < VDDR during device start-up | H | H | L | L |
| VDD-VSS < VDDR during device start-up | L | L | L | L |
| VDD-VSS < VDDR – VDDH after device start-up | H | L | L | L |
| VDD-VSS < VDDR – VDDH after device start-up | L | H | L | L |
| VDD-VSS < VDDR – VDDH after device start-up | H | H | L | L |
| VDD-VSS < VDDR – VDDH after device start-up | L | L | L | L |
| Condition (VDD>VDDR for all case below) | HI | LI | HO | LO |
|---|---|---|---|---|
| VHB-HS < VHBR during device start-up | H | L | L | L |
| VHB-HS < VHBR during device start-up | L | H | L | H |
| VHB-HS < VHBR during device start-up | H | H | L | H |
| VHB-HS < VHBR during device start-up | L | L | L | L |
| VHB-HS < VHBR – VHBH after device start-up | H | L | L | L |
| VHB-HS < VHBR – VHBH after device start-up | L | H | L | H |
| VHB-HS < VHBR – VHBH after device start-up | H | H | L | H |
| VHB-HS < VHBR – VHBH after device start-up | L | L | L | L |
The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output which is referenced to the HS pin and provides excellent delay matching with the low-side driver.
The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance, and high peak current capability of both outputs allow for efficient switching of the power MOSFETs. The low-side output stage is referenced to VSS and the high-side is referenced to HS.
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS node can swing below ground provided:
The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO operation mode. In normal mode when the VDD and VHB–HS are above UVLO threshold, the output stage is dependent on the states of the HI and LI pins. The output HO and LO will be low if input state is floating.