ZHCSK36 August 2019 DS160PR410
ADVANCE INFORMATION for pre-production products; subject to change without notice.
| PIN | I/O, TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ALL_DONE_N | 8 | O, 3.3-V open drain | Indicates the completion of a valid EEPROM register load operation when in SMBus/I2C Master Mode (EN_SMB = L1):
High: External EEPROM load failed or incomplete Low: External EEPROM load successful and complete When in SMBus/I2C slave mode (EN_SMB = L3), this output will be High-Z until READ_EN_N is driven low, at which point ALL_DONE_N will be driven low. External pullup required for operation. TI recommends a 4.7k value. |
| EN_SMB | 2 | I, 4-level | Four-level control input used to select SMBus / I2C or Pin control.
The four defined levels are: L0: Pin mode L1: I2C or SMBus Master Mode L2: RESERVED L3: I2C or SMBus Slave Mode |
| EQ0_ADDR0 | 7 | I, 4-level | The 4-Level Control Input pins of DS160PR410 is defined according to Table 3.
If EN_SMB = L1 or L3, the pins are used to set the I2C or SMBus address of the device. The pin state is read on power up and decoded according to Table 4. If EN_SMB = L0, the pins are decoded at power up to control the CTLE boost setting according to Table 1. |
| EQ1_ADDR1 | 6 | I, 4-level | |
| GAIN | 5 | I, 4-level | Sets DC gain of CTLE at power up.
L0: Reserved L1: Reserved L2: 0 dB L3: 3.5 dB |
| GND | EP | P | EP is the Exposed Pad at the bottom of the WQFN package. It is used as the GND return for the device. The EP should be connected to ground plane(s) through low resistance path. A via array provides a low impedance path to GND, and also improves thermal dissipation. |
| NC | 1, 14, 15, 27, 28 | — | No connect |
| PWDN1 | 21 | I, 3.3-V LVCMOS | Two-level logic controlling the operating state of the redriver.
High: Power down for channels 0 and 1 Low: Power up, normal operation for channels 0 and 1. |
| PWDN2 | 25 | I, 3.3-V LVCMOS | Two-level logic controlling the operating state of the redriver.
High: Power down for channels 2 and 3 Low: Power up, normal operation for channels 2 and 3. |
| READ_EN_N | 22 | I, 3.3-V LVCMOS | SMBus / I2C Master Mode (with EN_SMB = L1): When asserted low, initiates the SMBus / I2C master mode EEPROM read function. When the EEPROM read is complete (indicated by assertion of ALL_DONE_N low), this pin can be held low for normal device operation.
SMBus / I2C Slave Mode (with EN_SMB = L3): When asserted low, this causes the device to be held in reset (I2C state machine reset and register reset). This pin should be pulled high to 3.3 V with a external 4.7-kΩ pullup for normal operation in SMBus / I2C Slave Mode or in pin control mode. |
| RSVD | 24 | — | Reserved use for TI. The pin must be left floating (NC). |
| RX_DET | 26 | I, 4-level | The RX_DET pin controls the receiver detect function. Depending on the input level, a 50-Ω or >50-kΩ termination to the power rail is enabled. See Table 2 for details. |
| RX0N | 30 | I | Inverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. Channel 0. |
| RX0P | 29 | I | Noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. Channel 0. |
| RX1N | 33 | I | Inverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. Channel 1. |
| RX1P | 32 | I | Noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. Channel 1. |
| RX2N | 37 | I | Inverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. Channel 2. |
| RX2P | 36 | I | Noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. Channel 2. |
| RX3N | 40 | I | Inverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. Channel 3. |
| RX3P | 39 | I | Noninverting differential inputs to the equalizer. An on-chip, 100-Ω termination resistor connects RXP to RXN. Channel 3. |
| SCL | 3 | I/O, 3.3-V LVCMOS, open drain | SMBus / I2C clock input / open-drain output. External 1-kΩ to 5-kΩ pullup resistor is required as per SMBus / I2C interface standard. This pin is 3.3-V tolerant. |
| SDA | 4 | I/O, 3.3-V LVCMOS, open drain | SMBus / I2C data input / open-drain clock output. External 1-kΩ to 5-kΩ pullup resistor is required as per SMBus interface standard. This pin is 3.3-V tolerant. |
| TX0N | 19 | O | Inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 0. |
| TX0P | 20 | O | Noninverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 0. |
| TX1N | 16 | O | Inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 1. |
| TX1P | 17 | O | Noninverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 1. |
| TX2N | 12 | O | Inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 2. |
| TX2P | 13 | O | Noninverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 2. |
| TX3N | 9 | O | Inverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 3. |
| TX3P | 10 | O | Noninverting 50-Ω driver outputs. Compatible with AC-coupled differential inputs. Also used for RX detection at power up. Channel 3. |
| VDD | 31, 34, 35, 38 | P | Power supply pins. VDD = 3.3 V ±10%. The VDD pins on this device should be connected through a low-resistance path to the board VDD plane. |
| VOD | 23 | I, 4-level | Sets TX VOD setting at power up.
L0: –6 dB L1: –3.5 dB L2: 0 dB L3: –1.6 dB |
| VREG | 11, 18 | P | Internal voltage regulator output. Must add decoupling caps of 0.1 µF near each pins. The regulator is only for internal use. Do not use to power any external components. |