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SNAS395F December 2007 – October 2016 DAC121C081 , DAC121C085

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DDC|6
- MPDS124I
NGF|6
- MPDS394

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

	MIN	MAX	UNIT
Supply voltage, V_A	–0.3	6.5	V
Voltage on any input pin	–0.3	6.5	V
Input current at any pin⁽⁴⁾		±10	mA
Package input current⁽⁴⁾		±20	mA
Power consumption at T_A = 25°C		See⁽⁵⁾
Junction temperature, T_J		150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20-mA maximum package input current ratings limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature (T_A), and can be calculated using the formula PDMAX = (T_Jmax − T_A) / θ_JA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (for example, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

7.2 ESD Ratings

				VALUE	UNIT
DAC081C081 in NGF Package
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001	All pins except 2 and 3	±2500	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001	Pins 2 and 3	±5000
		Charged-device model (CDM), per JEDEC specification JESD22-C101	All pins except 2 and 3	±1000
			Pins 2 and 3	±1000
		Machine model (MM)	All pins except 2 and 3	±250
		Machine model (MM)	Pins 2 and 3	±350
DAC081C081 in DDC Package
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001	All pins except 4 and 5	±2500	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001	Pins 4 and 5	±5000
		Charged-device model (CDM), per JEDEC specification JESD22-C101	All pins except 4 and 5	±1000
			Pins 4 and 5	±1000
		Machine model (MM)	All pins except 4 and 5	±250
		Machine model (MM)	Pins 4 and 5	±350
DAC081C085 in DGK Package
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001	All pins except 3 and 4	±2500	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001	Pins 3 and 4	±5000
		Charged-device model (CDM), per JEDEC specification JESD22-C101	All pins except 3 and 4	±1000
			Pins 3 and 4	±1000
		Machine model (MM)	All pins except 3 and 4	±250
		Machine model (MM)	Pins 3 and 4	±350

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Operating temperature, T_A	−40	125	°C
Supply voltage, V_A	2.7	5.5	V
Reference voltage, V_REFIN	1	V_A	V
Digital input voltage⁽²⁾	0	5.5	V
Output load	0	1500	pF

(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.

(2) The inputs are protected as shown in the following. Input voltage magnitudes up to 5.5 V, regardless of V_A, will not cause errors in the conversion result. For example, if V_A is 3 V, the digital input pins can be driven with a 5-V logic device.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾⁽³⁾		DAC121C081		DAC121C085	UNIT
		NGF (WSON)	DDC (SOT)	DGK (VSSOP)
		6 PINS	6 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	190	250	240	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) Soldering process must comply with Texas Instruments' Reflow Temperature Profile Specifications, SNOA549.

(3) Reflow temperature profiles are different for lead-free packages.

7.5 Electrical Characteristics

The following specifications apply for V_A = 2.7 V to 5.5 V, V_REF = V_A, C_L = 200 pF to GND, input code range 48 to 4047. All Maximum and Minimum limits apply for T_MIN ≤ T_A ≤ T_MAX and all Typical limits are at T_A = 25°C, unless otherwise specified.⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN	TYP⁽³⁾	MAX⁽³⁾	UNIT
STATIC PERFORMANCE
INL	Resolution			12			Bits
	Monotonicity			12			Bits
	Integral Non-Linearity				2.2	8	LSB
	Integral Non-Linearity			–8	–1.5		LSB
DNL	Differential Non-Linearity				0.18	0.6	LSB
DNL	Differential Non-Linearity			–0.5	–0.12		LSB
ZE	Zero Code Error	I_OUT = 0			1.1	10	mV
FSE	Full-Scale Error	I_OUT = 0			–0.1	−0.7	%FSR
GE	Gain Error	All ones Loaded to DAC register			–0.2	−0.7	%FSR
ZCED	Zero Code Error Drift				–20		µV/°C
TC GE	Gain Error Tempco	V_A = 3 V			–0.7		ppm FSR/°C
TC GE	Gain Error Tempco	V_A = 5 V			–1		ppm FSR/°C
ANALOG OUTPUT CHARACTERISTICS (V_OUT)
	Output voltage range⁽⁴⁾	DAC121C085		0		V_REF	V
	Output voltage range⁽⁴⁾	DAC121C081		0		V_A	V
ZCO	Zero code output	V_A = 3 V, I_OUT = 200 µA			1.3		mV
ZCO	Zero code output	V_A = 5 V, I_OUT = 200 µA			7		mV
FSO	Full scale output	V_A = 3 V, I_OUT = 200 µA			2.984		V
FSO	Full scale output	V_A = 5 V, I_OUT = 200 µA			4.989		V
I_OS	Output short-circuit current (I_SOURCE)	V_A = 3 V, V_OUT = 0 V, Input Code = FFFh.			56		mA
I_OS	Output short-circuit current (I_SOURCE)	V_A = 5 V, V_OUT = 0 V, Input Code = FFFh.			69		mA
I_OS	Output short-circuit current (I_SINK)	V_A = 3 V, V_OUT = 3 V, Input Code = 000h.			–52		mA
I_OS	Output short-circuit current (I_SINK)	V_A = 5 V, V_OUT = 5 V, Input Code = 000h.			–75		mA
I_O	Continuous output current⁽⁴⁾	Available on the DAC output				11	mA
C_L	Maximum load capacitance	R_L = ∞			1500		pF
C_L	Maximum load capacitance	R_L = 2 kΩ			1500		pF
Z_OUT	DC output impedance				7.5		Ω
REFERENCE INPUT CHARACTERISTICS (DAC121C085 only)
V_REF	Input range minimum			1	0.2		V
	Input range maximum					V_A	V
	Input impedance				120		kΩ
LOGIC INPUT CHARACTERISTICS (SCL, SDA)
V_IH	Input high voltage			0.7 × V_A			V
V_IL	Input low voltage					0.3 × V_A	V
I_IN	Input current					±1	µA
C_IN	Input pin capacitance⁽⁴⁾					3	pF
V_HYST	Input hysteresis			0.1 × V_A			V
LOGIC INPUT CHARACTERISTICS (ADR0, ADR1)
V_IH	Input high voltage			V_A- 0.5			V
V_IL	Input low voltage					0.5	V
I_IN	Input current					±1	µA
LOGIC OUTPUT CHARACTERISTICS (SDA)
V_OL	Output low voltage	I_SINK = 3 mA				0.4	V
V_OL	Output low voltage	I_SINK = 6 mA				0.6	V
I_OZ	High-impedence output leakage current					±1	µA
POWER REQUIREMENTS
V_A	Supply voltage minimum			2.7			V
V_A	Supply voltage maximum					5.5	V
Normal -- V_OUT set to midscale. 2-wire interface quiet (SCL = SDA = V_A). (output unloaded)
I_{ST_VA-1}	V_ADAC121C081 supply current	V_A = 2.7 V to 3.6 V			105	156	µA
I_{ST_VA-1}	V_ADAC121C081 supply current	V_A = 4.5 V to 5.5 V			132	214	µA
I_{ST_VA-5}	V_ADAC121C085 supply current	V_A = 2.7 V to 3.6 V			86	118	µA
I_{ST_VA-5}	V_ADAC121C085 supply current	V_A = 4.5 V to 5.5 V			98	152	µA
I_{ST_VREF}	V_REF supply current (DAC121C085 only)	V_A = 2.7 V to 3.6 V			37	43	µA
I_{ST_VREF}	V_REF supply current (DAC121C085 only)	V_A = 4.5 V to 5.5 V			53	61	µA
P_ST	Power consumption (V_A and V_REF for DAC121C085)⁽²⁾	V_A = 3 V			380		µW
P_ST	Power consumption (V_A and V_REF for DAC121C085)⁽²⁾	V_A = 5 V			730		µW
Continuous Operation -- 2-wire interface actively addressing the DAC and writing to the DAC register. (output unloaded)
I_{CO_VA-1}	V_ADAC121C081 supply current	f_SCL=400 kHz	V_A = 2.7 V to 3.6 V		134	220	µA
		f_SCL=400 kHz	V_A = 4.5 V to 5.5 V		192	300	µA
		f_SCL = 3.4 MHz	V_A = 2.7 V to 3.6 V		225	320	µA
		f_SCL = 3.4 MHz	V_A = 4.5 V to 5.5 V		374	500	µA
I_{CO_VA-5}	V_ADAC121C085 supply current	f_SCL= 400 kHz	V_A = 2.7 V to 3.6 V		101	155	µA
		f_SCL= 400 kHz	V_A = 4.5 V to 5.5 V		142	220	µA
		f_SCL = 3.4 MHz	V_A = 2.7 V to 3.6 V		193	235	µA
		f_SCL = 3.4 MHz	V_A = 4.5 V to 5.5 V		325	410	µA
I_{CO_VREF}	V_REF supply current (DAC121C085 only)		V_A = 2.7 V to 3.6 V		33.5	55	µA
I_{CO_VREF}	V_REF supply current (DAC121C085 only)		V_A = 4.5 V to 5.5 V		49.5	71.4	µA
P_CO	Power consumption (V_A and V_REF for DAC121C085)	f_SCL = 400 kHz	V_A = 3 V		480		µW
		f_SCL = 400 kHz	V_A = 5 V		1.06		mW
		f_SCL= 3.4 MHz	V_A = 3 V		810		µW
		f_SCL= 3.4 MHz	V_A = 5 V		2.06		mW
Power Down -- 2-wire interface quiet (SCL = SDA = V_A) after PD mode written to DAC register. (output unloaded)
I_PD	Supply current (V_A and V_REF for DAC121C085)	All power-down modes	V_A = 2.7 V to 3.6		0.13	1.52	µA
I_PD	Supply current (V_A and V_REF for DAC121C085)	All power-down modes	V_A = 4.5 V to 5.5 V		0.15	3.25	µA
P_PD	Power consumption (V_A and V_REF for DAC121C085)	All power-down modes	V_A = 3 V		0.5		µW
P_PD	Power consumption (V_A and V_REF for DAC121C085)	All power-down modes	V_A = 5 V		0.9		µW

(1) Values shown in this table are design targets and are subject to change before product release.

7.6 AC and Timing Characteristics

The following specifications apply for V_A = 2.7 V to 5.5 V, V_REF = V_A, R_L = Infinity, C_L = 200 pF to GND. All Maximum and Minimum limits apply for T_MIN ≤ T_A ≤ T_MAX and all Typical limits are at T_A = 25°C, unless otherwise specified.⁽¹⁾

PARAMETER		TEST CONDITIONS⁽⁷⁾	MIN	TYP⁽³⁾	MAX⁽⁷⁾⁽³⁾	UNIT
t_s	Output Voltage Settling Time⁽⁴⁾	400h to C00h code change R_L = 2 kΩ, C_L = 200 pF		6	8.5	µs
SR	Output Slew Rate			1		V/µs
	Glitch Impulse	Code change from 800h to 7FFh		12		nV-sec
	Digital Feedthrough			0.5		nV-sec
	Multiplying Bandwidth⁽⁶⁾	V_REF = 2.5 V ± 0.1 Vpp		160		kHz
	Total Harmonic Distortion⁽⁶⁾	V_REF = 2.5 V ± 0.1 Vpp input frequency = 10 kHz		70		dB
t_WU	Wake-Up Time	V_A = 3 V		0.8		µs
t_WU	Wake-Up Time	V_A = 5 V		0.5		µs
DIGITAL TIMING SPECS (SCL, SDA)
f_SCL	Serial Clock Frequency	Standard Mode			100	kHz
		Fast Mode			400	kHz
		High Speed Mode, C_b = 100 pF			3.4	MHz
		High Speed Mode, C_b = 400 pF			1.7	MHz
t_LOW	SCL Low Time	Standard Mode	4.7			µs
		Fast Mode	1.3			µs
		High Speed Mode, C_b = 100 pF	160			ns
		High Speed Mode, C_b = 400 pF	320			ns
t_HIGH	SCL High Time	Standard Mode	4			µs
		Fast Mode	0.6			µs
		High Speed Mode, C_b = 100 pF	60			ns
		High Speed Mode, C_b = 400 pF	120			ns
t_SU;DAT	Data Setup Time	Standard Mode	250			ns
		Fast Mode	100
		High Speed Mode	10
t_HD;DAT	Data Hold Time	Standard Mode	0		3.45	µs
		Fast Mode	0		0.9	µs
		High Speed Mode, C_b = 100 pF	0		70	ns
		High Speed Mode, C_b = 400 pF	0		150	ns
t_SU;STA	Setup time for a start or a repeated start condition	Standard Mode	4.7			µs
		Fast Mode	0.6			µs
		High Speed Mode	160			ns
t_HD;STA	Hold time for a start or a repeated start condition	Standard Mode	4			µs
		Fast Mode	0.6			µs
		High Speed Mode	160			ns
t_BUF	Bus free time between a stop and start condition	Standard Mode	4.7			µs
t_BUF	Bus free time between a stop and start condition	Fast Mode	1.3			µs
t_SU;STO	Setup time for a stop condition	Standard Mode	4			µs
		Fast Mode	0.6			µs
		High Speed Mode	160			ns
t_rDA	Rise time of SDA signal	Standard Mode			1000	ns
		Fast Mode	20+0.1C_b		300
		High Speed Mode, C_b = 100 pF	10		80
		High Speed Mode, C_b = 400 pF	20		160
t_fDA	Fall time of SDA signal	Standard Mode			250	ns
		Fast Mode	20+0.1C_b		250
		High Speed Mode, C_b = 100 pF	10		80
		High Speed Mode, C_b = 400 pF	20		160
t_rCL	Rise time of SCL signal	Standard Mode			1000	ns
		Fast Mode	20+0.1C_b		300
		High Speed Mode, C_b = 100 pF	10		40
		High Speed Mode, C_b = 400 pF	20		80
t_rCL1	Rise time of SCL signal after a repeated start condition and after an acknowledge bit.	Standard Mode			1000	ns
		Fast Mode	20+0.1C_b		300
		High Speed Mode, C_b = 100 pF	10		80
		High Speed Mode, C_b = 400 pF	20		160
t_fCL	Fall time of a SCL signal	Standard Mode			300	ns
		Fast Mode	20+0.1C_b		300
		High Speed Mode, C_b = 100 pF	10		40
		High Speed Mode, C_b = 400 pF	20		80
C_b	Capacitive load for each bus line (SCL and SDA)				400	pF
t_SP	Pulse Width of spike suppressed⁽⁵⁾⁽⁴⁾	Fast Mode			50	ns
t_SP	Pulse Width of spike suppressed⁽⁵⁾⁽⁴⁾	High Speed Mode			10	ns
t_outz	SDA output delay (see the Additional Timing Information section)	Fast Mode		87	270	ns
t_outz		High Speed Mode		38	60	ns

(1) Values shown in this table are design targets and are subject to change before product release.

(2) To ensure accuracy, it is required that V_A and V_REF be well bypassed.

(3) Typical figures are at T_J = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing Quality Level).

(4) This parameter is specified by design and/or characterization and is not tested in production.

(5) Spike suppression filtering on SCL and SDA will supress spikes that are less than 50 ns for standard-fast mode and less than 10ns for hs-mode.

(6) Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the DAC Register will digitally attenuate the signal at Vout.

(7) C_b refers to the capacitance of one bus line. C_b is expressed in pF units.