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ZHCSDL9A December 2014 – March 2015 CSD97395Q4M

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DPC|8

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

T_A = 25°C (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
	V_IN to P_GND	–0.3	30	V
	V_SW to P_GND , V_IN to V_SW	–0.3	30	V
	V_SW to P_GND, V_IN to V_SW (<10 ns)	–7	33	V
	V_DD to P_GND	–0.3	6	V
	PWM, SKIP# to P_GND	–0.3	6	V
	BOOT to P_GND	–0.3	35	V
	BOOT to P_GND (<10 ns)	–2	38	V
	BOOT to BOOT_R	–0.3	6	V
	BOOT to BOOT_R (duty cycle <0.2%)		8	V
P_D	Power Dissipation		8	W
T_J	Operating Temperature	–40	150	°C
T_stg	Storage temperature range	–55	150	°C

(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE		UNIT
V_(ESD)	Electrostatic discharge	Human Body Model (HBM)⁽¹⁾	±2000		V
V_(ESD)	Electrostatic discharge	Charged Device Model (CDM)⁽²⁾	±500		V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

T_A = 25°C (unless otherwise noted)

			MIN	MAX	UNIT
V_DD	Gate Drive Voltage		4.5	5.5	V
V_IN	Input Supply Voltage ⁽¹⁾			24	V
I_OUT	Continuous Output Current	V_IN = 12 V, V_DD = 5 V, V_OUT = 1.8 V, ƒ_SW = 500 kHz, L_OUT = 0.29 µH⁽²⁾		25	A
I_OUT-PK	Peak Output Current⁽³⁾			60	A
ƒ_SW	Switching Frequency	C_BST = 0.1 µF (min)		2000	kHz
	On-Time Duty Cycle			85%
	Minimum PWM On-Time		40		ns
	Operating Temperature		–40	125	°C

(1) Operating at high V_IN can create excessive AC voltage overshoots on the switch node (V_SW) during MOSFET switching transients. For reliable operation, the switch node (V_SW) to ground voltage must remain at or below the Absolute Maximum Ratings.

(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins.

(3) System conditions as defined in Note 2. Peak Output Current is applied for t_p = 10 ms, duty cycle ≤1%

6.4 Thermal Information

T_A = 25°C (unless otherwise noted)

THERMAL METRIC		MIN	TYP	MAX	UNIT
R_θJC	Junction-to-Case Thermal Resistance (Top of package)⁽¹⁾			22.8	°C/W
R_θJB	Junction-to-Board Thermal Resistance⁽²⁾			2.5	°C/W

(1) R_θJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inch x 1.5 inch, 0.06 inch (1.52 mm) thick FR4 board.

(2) R_θJB value based on hottest board temperature within 1 mm of the package.

6.5 Electrical Characteristics

T_A = 25°C, V_DD = POR to 5.5V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
P_LOSS
Power Loss⁽¹⁾		V_IN = 12 V, V_DD = 5 V, V_OUT = 1.8 V, I_OUT = 15 A, ƒ_SW = 500 kHz, L_OUT = 0.29 µH, T_J = 25°C		2.3		W
Power Loss⁽²⁾		V_IN = 19 V, V_DD = 5 V, V_OUT = 1.8 V, I_OUT = 15 A, ƒ_SW = 500 kHz, L_OUT = 0.29 µH, T_J = 25°C		2.5		W
Power Loss⁽²⁾		V_IN = 19 V, V_DD = 5 V, V_OUT = 1.8 V, I_OUT = 15 A, ƒ_SW = 500 kHz, L_OUT = 0.29 µH, T_J = 125°C		2.8		W
V_IN
I_Q	V_IN Quiescent Current	PWM=Floating, V_DD = 5 V, V_IN= 24 V			1	µA
V_DD
I_DD	Standby Supply Current	PWM = Float, SKIP# = V_DD or 0 V		130		µA
I_DD	Standby Supply Current	SKIP# = Float		8		µA
I_DD	Operating Supply Current	PWM = 50% Duty cycle, ƒ_SW = 500 kHz		8.2		mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
V_DD Rising	Power-On Reset				4.15	V
V_DD Falling	UVLO		3.7			V
	Hysteresis			0.2		mV
PWM AND SKIP# I/O SPECIFICATIONS
R_I	Input Impedance	Pull Up to V_DD		1700		kΩ
R_I	Input Impedance	Pull Down (to GND)		800		kΩ
V_IH	Logic Level High		2.65			V
V_IL	Logic Level Low				0.6
V_IH	Hysteresis			0.2
V_TS	Tri-State Voltage		1.3		2
t_THOLD(off1)	Tri-state Activation Time (falling) PWM⁽²⁾			60		ns
t_THOLD(off2)	Tri-state Activation Time (rising) PWM⁽²⁾			60		ns
t_TSKF	Tri-state Activation Time (falling) SKIP#⁽²⁾			1		µs
t_TSKR	Tri-state Activation Time (rising) SKIP# ⁽²⁾			1		µs
t_3RD(PWM)	Tri-state Exit Time PWM⁽²⁾				100	ns
t_3RD(SKIP#)	Tri-state Exit Time SKIP#⁽²⁾				50	µs
BOOTSTRAP SWITCH
V_FBST	Forward Voltage	I_F = 10 mA		120	240	mV
I_RLEAK	Reverse Leakage⁽²⁾	V_BST – V_DD = 25 V			2	µA

(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins.

(2) Specified by design.