SCAS877F May 2009 – January 2016 CDCLVP1216
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: LVCMOS Input
- 6.6 Electrical Characteristics: Differential Input
- 6.7 Electrical Characteristics: LVPECL Output, at VCC = 2.375 V to 2.625 V
- 6.8 Electrical Characteristics: LVPECL Output, at VCC = 3 V to 3.6 V
- 6.9 Timing Requirements, at VCC = 2.375 V to 2.625 V
- 6.10 Timing Requirements, at VCC = 3 V to 3.6 V
- 6.11 Pin Characteristics
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Applications and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
- 14Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購信息
8 Detailed Description
8.1 Overview
The CDCLVP1216 uses an open emitter follower stage for its LVPECL outputs. Therefore, proper output biasing and termination are required to ensure correct operation of the device and to maximize output signal integrity. The proper termination for LVPECL outputs is a 50 Ω to (VCC – 2) V, but this DC voltage is not readily available on PCB. Therefore, a Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled configurations. These configurations are shown in Figure 12 (a and b) for VCC = 2.5 V and Figure 13 (a and b) for VCC = 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the receiver end. If the supply voltage for the driver and receiver is different, AC coupling is required.
8.2 Functional Block Diagram
8.3 Feature Description
The CDCLVP1216 is a low additive jitter universal to LVPECL fan-out buffer with 2 selectable inputs. The small package, low output skew, and low additive jitter make for a flexible device in demanding applications.
8.4 Device Functional Modes
The two inputs of the CDCLVP1216 are internally muxed together and can be selected via the control pin. Unused inputs and outputs can be left floating to reduce overall component cost. Both AC and DC coupling schemes can be used with the CDCLVP1216 to provide greater system flexibility.
8.4.1 LVPECL Output Termination
Figure 13. LVPECL Output DC and AC Termination for VCC = 3.3 V
Table 1. Input Selection Table
| IN_SEL | ACTIVE CLOCK INPUT |
|---|---|
| 0 | INP0, INN0 |
| 1 | INP1, INN1 |
8.4.2 Input Termination
The CDCLVP1216 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 14 shows how to DC couple an LVCMOS input to the CDCLVP1216. The series resistance (RS) must be placed close to the LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver output impedance.
Figure 14. DC-Coupled LVCMOS Input to CDCLVP1216
Figure 15 shows how to DC couple LVDS inputs to the CDCLVP1216. Figure 16 and Figure 17 describe the method of DC coupling LVPECL inputs to the CDCLVP1216 for VCC = 2.5 V and VCC = 3.3 V, respectively.
Figure 15. DC-Coupled LVDS Inputs to CDCLVP1216
Figure 17. DC-Coupled LVPECL Inputs to CDCLVP1216 (VCC = 3.3 V)
Figure 18 and Figure 19 show the technique of AC coupling differential inputs to the CDCLVP1216 for
VCC = 2.5 V and VCC = 3.3 V, respectively. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.
Figure 18. AC-Coupled Differential Inputs to CDCLVP1216 (VCC = 2.5 V)
Figure 19. AC-Coupled Differential Inputs to CDCLVP1216 (VCC = 3.3 V)