SLUSA44A March 2010 – July 2015
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Output Voltage Regulation
- 7.3.2 Output Current Regulation
- 7.3.3 Power Up
- 7.3.4 Enable and Disable Charging
- 7.3.5 Automatic Internal Soft-Start Charger Current
- 7.3.6 Converter Operation
- 7.3.7 Synchronous and Nonsynchronous Operation
- 7.3.8 Input Overvoltage Protection (ACOV)
- 7.3.9 Output Overvoltage Protection
- 7.3.10 Cycle-by-Cycle Charge Overcurrent Protection
- 7.3.11 Thermal Shutdown Protection
- 7.3.12 Temperature Qualification
- 7.3.13 CE (Charge Enable)
- 7.3.14 PG Output
- 7.3.15 Charge Status Outputs
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RVA|16
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RVA|16
訂購(gòu)信息
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage (2) | VCC, SRP, SRN, STAT, PG, CE | –0.3 | 33 | V |
| PH | –2 | 33 | ||
| VFB(3) | –0.3 | 16 | ||
| REGN, LODRV, TS | –0.3 | 7 | ||
| BTST, HIDRV with respect to GND | –0.3 | 39 | ||
| VREF, ISET | –0.3 | 3.6 | ||
| Maximum difference voltage | SRP–SRN | –0.5 | 0.5 | V |
| Temperature | Junction, TJ | –40 | 155 | °C |
| Storage, Tstg | –55 | 155 | ||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult the Package Option Addendum at the end of the data sheet for thermal limitations and considerations.
(3) Must have a series resistor between output to VFB if output voltage is expected to be greater than 16 V. Usually the resistor-divider top resistor will take care of this.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage (with respect to GND) |
VCC, SRP, SRN, STAT, PG, CE | –0.3 | 28 | V |
| PH | –2 | 30 | ||
| VFB | –0.3 | 14 | ||
| REGN, LODRV, TS | –0.3 | 6.5 | ||
| BTST, HIDRV with respect to GND | –0.3 | 34 | ||
| ISET | –0.3 | 3.3 | ||
| VREF | 3.3 | |||
| Maximum difference voltage | SRP–SRN | –0.2 | 0.2 | V |
| Junction temperature, TJ | 0 | 125 | °C | |
6.4 Thermal Information
| THERMAL METRIC(1) | bq24640 | UNIT | |
|---|---|---|---|
| RVA (VQFN) | |||
| 16 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 43.8 | °C/W |
| RθJC(top) | Junction-to-case(top) thermal resistance | 81 | °C/W |
| RθJB | Junction-to-board thermal resistance | 16 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.6 | °C/W |
| ψJB | Junction-to-board characterization parameter | 15.77 | °C/W |
| RθJC(bot) | Junction-to-case(bottom) thermal resistance | 4 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
5 V ≤ V(VCC) ≤ 28 V, 0°C < T< 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| OPERATING CONDITIONS | ||||||
| VVCC_OP | VCC input voltage operating range | 5 | 28 | V | ||
| QUIESCENT CURRENTS | ||||||
| IOUT | Total output discharge current (sum of currents into VCC, BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1V | VUVLO < VVCC < VSRN (sleep mode) | 15 | µA | ||
| IAC | Adapter supply current into VCC pin | VVCC > VSRN, VVCC > VUVLO, CE = LOW |
1 | 1.5 | mA | |
| VVCC > VSRN, VVCC > VVCCLOWV, CE = HIGH, charge done |
2 | 5 | ||||
| VVCC > VSRN, VVCC > VVCCLOWV, CE = HIGH, Charging, Qg_total = 20 nC, VVCC = 20 V |
25 | |||||
| CHARGE VOLTAGE REGULATION | ||||||
| VFB | Feedback regulation voltage | 2.1 | V | |||
| Charge voltage regulation accuracy | TJ = 0°C to 85°C | –0.5% | 0.5% | |||
| TJ = –40°C to 125°C | –0.7% | 0.7% | ||||
| IVFB | Leakage current into VFB pin | VFB = 2.1 V | 100 | nA | ||
| CURRENT REGULATION | ||||||
| VISET1 | ISET voltage range | 2 | V | |||
| VIREG_CHG | SRP-SRN current sense voltage range | VIREG_CHG = VSRP – VSRN | 100 | mV | ||
| KISET1 | Charge current set factor (amps of charge current per volt on ISET pin) | RSENSE = 10 mΩ | 5 | A/V | ||
| Charge current regulation accuracy | VIREG_CHG = 40 mV | –3% | 3% | |||
| VIREG_CHG = 20 mV | –5% | 5% | ||||
| VIREG_CHG = 5 mV | –25% | 25% | ||||
| VIREG_CHG = 1.5 mV | –50% | 50% | ||||
| IISET | Leakage current into ISET pin | VISET1 = 2 V | 100 | nA | ||
| INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO) | ||||||
| VUVLO | AC undervoltage rising threshold | Measure on VCC | 3.65 | 3.85 | 4 | V |
| VUVLO_HYS | AC undervoltage hysteresis, falling | 350 | mV | |||
| VCC LOWV COMPARATOR | ||||||
| VLOWV_FALL | Falling threshold, disable charge | Measure on VCC | 4.1 | V | ||
| VLOWV_RISE | Rising threshold, resume charge | 4.35 | 4.5 | V | ||
| SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION) | ||||||
| VSLEEP _FALL | Sleep falling threshold | VVCC – VSRN to enter sleep mdoe | 40 | 100 | 150 | mV |
| VSLEEP_HYS | Sleep hysteresis | 500 | mV | |||
| Sleep rising delay | VCC falling below SRN, Delay to pull up PG | 1 | µs | |||
| Sleep falling delay | VCC rising above SRN, Delay to pull down PG | 30 | ms | |||
| Sleep rising shutdown deglitch | VCC falling below SRN, Delay to enter sleep mode | 100 | ms | |||
| Sleep falling powerup deglitch | VCC rising above SRN, Delay to exit sleep mode | 30 | ms | |||
| OUT OVERVOLTAGE COMPARATOR | ||||||
| VOV_RISE | Overvoltage rising threshold | As percentage of VVFB | 104% | |||
| VOV_FALL | Overvoltage falling threshold | As percentage of VVFB | 102% | |||
| INPUT OVERVOLTAGE COMPARATOR (ACOV) | ||||||
| VACOV | AC overvoltage rising threshold | Measured on VCC | 31 | 32 | 33 | V |
| VACOV_HYS | AC overvoltage falling hysteresis | 1 | V | |||
| AC overvoltage rising deglitch | Delay to disable charge | 1 | ms | |||
| AC overvoltage falling deglitch | Delay to resume charge | 1 | ms | |||
| THERMAL SHUTDOWN COMPARATOR | ||||||
| TSHUT | Thermal shutdown rising temperature | Temperature Increasing | 145 | °C | ||
| TSHUT_HYS | Thermal shutdown hysteresis | 15 | °C | |||
| Thermal shutdown rising deglitch | Temperature Increasing | 100 | µs | |||
| Thermal shutdown falling deglitch | Temperature Decreasing | 10 | ms | |||
| THERMISTOR COMPARATOR | ||||||
| VLTF | Cold temperature rising threshold | As percentage to VVREF | 72.5% | 73.5% | 74.5% | |
| VLTF_HYS | Rising hysteresis | As percentage to VVREF | 0.2% | 0.4% | 0.6% | |
| VHTF | Hot temperature rising threshold | As percentage to VVREF | 36.4% | 37% | 37.6% | |
| VTCO | Cutoff temperature rising threshold | As percentage to VVREF | 33.7% | 34.4% | 35.1% | |
| Deglitch time for temperature out-of-range detection | VTS < VLTF, or VTS < VTCO, or VTS < VHTF | 400 | ms | |||
| Deglitch time for temperature in-valid-range detection | VTS > VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF | 20 | ms | |||
| CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE) | ||||||
| VOC | Charge overcurrent rising threshold | Current rising, in nonsynchronous mode, measure on V(SRP-SRN), VSRP < 2 V | 45.5 | mV | ||
| Current rising, as percentage of V(IREG_CHG), in synchronous mode, VSRP > 2.2 V | 160% | |||||
| Charge overcurrent threshold floor | Minimum OCP threshold in synchronous mode, measure on V(SRP-SRN), VSRP > 2.2 V | 50 | mV | |||
| Charge overcurrent threshold ceiling | Maximum OCP threshold in synchronous mode, measure on V(SRP-SRN), VSRP > 2.2 V | 180 | mV | |||
| CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE) | ||||||
| VISYNSET | Charge undercurrent falling threshold | Switch from CCM to DCM, VSRP > 2.2 V | 1 | 5 | 9 | mV |
| LOW CHARGE CURRENT COMPARATOR | ||||||
| VLC | Low charge current (average) falling threshold to force into nonsynchronous mode | Measure V(SRP-SRN) | 1.25 | mV | ||
| VLC_HYS | Low charge current rising hysteresis | 1.25 | mV | |||
| VLC_DEG | Deglitch on both edges | 1 | µs | |||
| VREF REGULATOR | ||||||
| VVREF_REG | VREF regulator voltage | VVCC > VUVLO (0–35 mA load) | 3.267 | 3.3 | 3.333 | V |
| IVREF_LIM | VREF current limit | VVREF = 0 V, VVCC > VUVLO | 35 | mA | ||
| REGN REGULATOR | ||||||
| VREGN_REG | REGN regulator voltage | VVCC > 10 V, CE = HIGH (0–40 mA load) | 5.7 | 6 | 6.3 | V |
| IREGN_LIM | REGN current limit | VREGN = 0 V, VVCC > VUVLO, CE = HIGH | 40 | mA | ||
| PWM HIGH-SIDE DRIVER (HIDRV) | ||||||
| RDS_HI_ON | High-side driver (HSD) turnon resistance | VBTST – VPH = 5.5 V | 3.3 | 6 | Ω | |
| RDS_HI_OFF | High-side driver turnoff resistance | VBTST – VPH = 5.5 V | 1 | 1.3 | Ω | |
| VBTST_REFRESH | Bootstrap refresh comparator threshold voltage | VBTST – VPH when low side refresh pulse is requested | 4 | 4.2 | V | |
| PWM LOW-SIDE DRIVER (LODRV) | ||||||
| RDS_LO_ON | Low-side driver (LSD) turnon resistance | 4.1 | 7 | Ω | ||
| RDS_LO_OFF | Low-side driver turnoff resistance | 1 | 1.4 | Ω | ||
| PWM DRIVERS TIMING | ||||||
| Driver Dead-Time | Dead time when switching between LSD and HSD, no load at LSD and HSD | 30 | ns | |||
| PWM OSCILLATOR | ||||||
| VRAMP_HEIGHT | PWM ramp height | As percentage of VCC | 7% | |||
| PWM switching frequency | 510 | 600 | 690 | kHz | ||
| INTERNAL SOFT START (8 STEPS TO REGULATION CURRENT ICHG) | ||||||
| Soft start steps | 8 | step | ||||
| Soft start step time | 1.6 | ms | ||||
| LOGIC IO PIN CHARACTERISTICS (CE, STAT, PG) | ||||||
| VIN_LO | CE input low threshold voltage | 0.8 | V | |||
| VIN_HI | CE input high threshold voltage | 2.1 | V | |||
| VBIAS_CE | CE input bias current | VCE = 3.3 nV (CE has internal 1-MΩ pulldown resistor) | 6 | μA | ||
| VOUT_LO | STAT, PG output low saturation voltage | Sink current = 5 mA | 0.5 | V | ||
| IOUT_HI | Leakage current | V = 32 V | 1.2 | μA | ||
6.6 Typical Characteristics
Table 1. Table of Graphs
| FIGURES | |
|---|---|
| Power Up (VREF, REGN, PG) | Figure 1 |
| Charge Enable and Disable | Figure 2 |
| Current Soft Start (CE = HIGH) | Figure 3 |
| Continuous Conduction Mode Switching Waveform | Figure 5 |
| Discontinuous Conduction Mode Switching Waveform | Figure 6 |
| Charge Profile | Figure 7 |
