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ZHCSRD5 December 2022 ADC3544

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- MPQF185C

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- QFND255H

訂購(gòu)信息

8.3.5.5 Output Bit Mapper

The output bit mapper allows to change the output bit order for any selected interface mode.

Figure 8-36 Output Bit Mapper

There is a two step process to change the output bit mapping and assemble the output data bus:

In parallel interface mode, the maximum output resolution is 18-bit, in serial interface mode the maximum output resolution is 20-bit. Each output bit of either channel has a unique identifier bit as shown in the Table 8-9. The MSB starts with bit D19. Depending on output resolution chosen, the LSB is D6 (14-bit) to D0 (20-bit). The previous sample is only needed in 2-w mode.
The bit mapper is then used to assemble the output sample. The following sections detail how to remap both a parallel and a serial output format.

Table 8-9 Unique identifier of each data bit

Bit	Previous sample (2w only)	Current sample
D19 (MSB)	0x2D	0x6D
D18	0x2C	0x6C
D17	0x27	0x67
D16	0x26	0x66
D15	0x25	0x65
D14	0x24	0x64
D13	0x1F	0x5F
D12	0x1E	0x5E
D11	0x1D	0x5D
D10	0x1C	0x5C
D9	0x17	0x57
D8	0x16	0x56
D7	0x15	0x55
D6	0x14	0x54
D5	0x0F	0x4F
D4	0x0E	0x4E
D3	0x0D	0x4D
D2	0x0C	0x4C
D1	0x07	0x47
D0 (LSB)	0x06	0x46

In parallel SDR mode, a data bit (with unique identifier) needs to be assigned to each output pin using the register addresses as shown in Figure 8-37. The example on the right shows the output data bus reversed to where the MSB starts on pin D2 instead of pin D15.

Figure 8-37 SDR output mapping (left) and example (right)

In parallel DDR mode, a data bit (with unique identifier) needs to be assigned to each output pin for both the rising and the falling edge of the DCLK using the register addresses as shown in Figure 8-38. D9 and D10 are used for 16 and 18-bit output. The example on the right shows the output data bus remapped to where the MSB starts on D17 instead of D11.

Figure 8-38 DDR output timing diagram with output mapping (left) and example (right)

In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses (0x39 to 0x60). When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.

2-wire mode: in this mode, both the current and the previous sample have to be used in the address space as shown in Figure 8-39. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.

Figure 8-39 2-wire output bit mapper

In the following example (Figure 8-40), the 16-bit 2-wire serial output is reordered to where pin D12 carries the 8 MSB and pin D11 carries 8 LSBs.

Figure 8-40 Example: 2-wire output mapping

1-wire mode: Only the ‘current’ sample needs to programmed in the address space.

Figure 8-41 1-wire output bit mapping