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ZHCSON7A July 2021 – October 2024 ADC12DJ800-Q1 , ADC12QJ800-Q1 , ADC12SJ800-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

AAV|144
- MPBGAM2C

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode

Forward error correction (FEC) is an optional feature in JESD204C and is supported by ADC12xJ800-Q1. Whereas CRC-12 mode can only detect errors on the link, FEC is able to detect and correct errors in order to improve the bit error rate (BER) for error-sensitive applications. Many applications can tolerate random bit errors, however some applications, such as an oscilloscope, rely on long error-free measurements in order to detect a certain response from the device under test (DUT). An error in these applications may result in a false-positive detection of the response. Enable FEC mode by setting SHMODE to 2.

A scrambled multiblock of 32 blocks (2048 bits) is input into the FEC parity bit generator to generate the 26-bit parity word. The parity word is sent in the sync header stream of the next multiblock. The receiver then calculates its own 26-bit parity word and calculates the difference between the locally generated and received parity word, called the syndrome of the received bits. If the syndrome is 0, then all bits are assumed to have been received correctly, while any value other than 0 indicates at least one error in either the data bits or the parity word. If the syndrome is non-zero, then it can be used to determine the most likely error and then correct the error. The minimum latency from a bit error to detection and correct of a bit error in the first bit of a multiblock is 58 blocks.

The mapping of the sync header stream when using FEC mode is shown in Table 6-12. FEC[x] corresponds to bit x of the 26-bit FEC word. The 00001 bit sequence at the end of the sync header stream is the pilot signal that is used to identify the end of a multiblock. It is possible for a 00001 sequence to appear in another location within the sync header stream in FEC mode, however it is improbable to see the 00001 sequence in the same location within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than one multiblock to find the end of a multiblock. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of an extended multiblock.

Table 6-12 Sync Header Stream Bit Mapping for FEC Mode

Bit	Function	Bit	Function	Bit	Function	Bit	Function
0	FEC[25]	8	FEC[17]	16	FEC[9]	24	FEC[2]
1	FEC[24]	9	FEC[16]	17	FEC[8]	25	FEC[1]
2	FEC[23]	10	FEC[15]	18	FEC[7]	26	FEC[0]
3	FEC[22]	11	FEC[14]	19	FEC[6]	27	0
4	FEC[21]	12	FEC[13]	20	FEC[5]	28	0
5	FEC[20]	13	FEC[12]	21	FEC[4]	29	0
6	FEC[19]	14	FEC[11]	22	EoEMB	30	0
7	FEC[18]	15	FEC[10]	23	FEC[3]	31	1

The FEC encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 26-bit parity word using the generator polynomial given by Equation 11. The 2048 scrambled input bits plus 26 parity bits forms a shortened (2074, 2048) binary cyclic code. The (2074, 2048) binary cyclic code is shortened from the cyclic Fire code (8687, 8661). This polynomial can correct up to a 9-bit burst error per multiblock.

Equation 11. g(x) = (x¹⁷+1)(x⁹+x⁴+1) == x²⁶+x²¹+x¹⁷+x⁹+x⁴+1

The full 26-bit FEC parity word generation is shown in Figure 6-10. The input is a 2048 bit sequence, built from the 32 scrambled blocks of a multiblock (sync header is not included). The 26-bit parity word, FEC[25:0], is taken from the S_x blocks after the full 2048 bit sequence is processed. The S_x blocks are initialized with 0s before processing each multiblock. For more information on the FEC parity word generation, refer to the JESD204C standard.

ADC12QJ800-Q1 ADC12DJ800-Q1 ADC12SJ800-Q1 FEC Parity Bit Generator

Figure 6-10 FEC Parity Bit Generator

FEC decoding and error correction are not covered here. For full details on FEC decoding and error correction, refer to the JESD204C standard.